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			<h1 id="tldr">TL;DR</h1>
<p><strong>Never use a lousy schematic editor again!</strong>
SKiDL is a simple module that lets you describe electronic circuits using Python.
The resulting Python program outputs a netlist that a PCB layout tool uses to
create a finished circuit board.</p>
<h3 id="contents">Contents</h3>
<ul>
<li><a href="#tldr">TL;DR</a>
        - <a href="#contents">Contents</a></li>
<li><a href="#introduction">Introduction</a></li>
<li><a href="#installation">Installation</a></li>
<li><a href="#basic-usage">Basic Usage</a><ul>
<li><a href="#accessing-skidl">Accessing SKiDL</a></li>
<li><a href="#finding-parts">Finding Parts</a><ul>
<li><a href="#command-line-searching">Command-line Searching</a><ul>
<li><a href="#interactive-mode-with-part-browsing">Interactive Mode with Part Browsing</a></li>
<li><a href="#output-formatting-and-options">Output Formatting and Options</a></li>
</ul>
</li>
<li><a href="#zyc-a-gui-search-tool">Zyc: A GUI Search Tool</a></li>
</ul>
</li>
<li><a href="#instantiating-parts">Instantiating Parts</a></li>
<li><a href="#connecting-pins">Connecting Pins</a></li>
<li><a href="#checking-for-errors">Checking for Errors</a></li>
<li><a href="#generating-a-netlist-or-pcb">Generating a Netlist or PCB</a></li>
</ul>
</li>
<li><a href="#going-deeper">Going Deeper</a><ul>
<li><a href="#basic-skidl-objects-parts-pins-nets-buses">Basic SKiDL Objects: Parts, Pins, Nets, Buses</a></li>
<li><a href="#creating-skidl-objects">Creating SKiDL Objects</a></li>
<li><a href="#finding-skidl-objects">Finding SKiDL Objects</a></li>
<li><a href="#copying-skidl-objects">Copying SKiDL Objects</a></li>
<li><a href="#accessing-part-pins-and-bus-lines">Accessing Part Pins and Bus Lines</a><ul>
<li><a href="#accessing-part-pins">Accessing Part Pins</a></li>
<li><a href="#accessing-bus-lines">Accessing Bus Lines</a></li>
</ul>
</li>
<li><a href="#making-connections">Making Connections</a></li>
<li><a href="#making-serial-parallel-and-tee-networks">Making Serial, Parallel, and Tee Networks</a></li>
<li><a href="#aliases">Aliases</a></li>
<li><a href="#units-within-parts">Units Within Parts</a></li>
<li><a href="#part-and-net-classes">Part and Net Classes</a><ul>
<li><a href="#individual-part-and-net-classes">Individual Part and Net Classes</a></li>
<li><a href="#hierarchical-part-and-net-class-inheritance">Hierarchical Part and Net Class Inheritance</a></li>
</ul>
</li>
<li><a href="#part-fields">Part Fields</a></li>
<li><a href="#hierarchy">Hierarchy</a><ul>
<li><a href="#method-1-subcircuit-decorator-with-interface-return">Method 1: SubCircuit Decorator with Interface Return</a></li>
<li><a href="#method-2-subcircuit-subclassing-with-io-attributes">Method 2: SubCircuit Subclassing with I/O Attributes</a></li>
<li><a href="#method-3-subcircuit-context-manager">Method 3: SubCircuit Context Manager</a></li>
</ul>
</li>
<li><a href="#libraries">Libraries</a></li>
<li><a href="#doodads">Doodads</a><ul>
<li><a href="#no-connects">No Connects</a></li>
<li><a href="#net-and-pin-drive-levels">Net and Pin Drive Levels</a></li>
<li><a href="#pin-net-bus-equivalencies">Pin, Net, Bus Equivalencies</a></li>
<li><a href="#disambiguating-part-pins-with-identical-names">Disambiguating Part Pins with Identical Names</a></li>
<li><a href="#part-like-access-of-subcircuit-modules">Part-Like Access of Subcircuit Modules</a></li>
<li><a href="#selectively-supressing-erc-messages">Selectively Supressing ERC Messages</a></li>
<li><a href="#customizable-erc-using-erc_assert">Customizable ERC Using <code>erc_assert()</code></a></li>
<li><a href="#handling-empty-footprints">Handling Empty Footprints</a></li>
<li><a href="#tags">Tags</a></li>
<li><a href="#configuration-file">Configuration File</a></li>
</ul>
</li>
</ul>
</li>
<li><a href="#going-really-deep">Going Really Deep</a><ul>
<li><a href="#ad-hoc-parts">Ad-Hoc Parts</a></li>
<li><a href="#circuit-objects">Circuit Objects</a></li>
<li><a href="#nodes">Nodes</a></li>
</ul>
</li>
<li><a href="#generating-a-schematic">Generating a Schematic</a><ul>
<li><a href="#svg-schematics">SVG Schematics</a></li>
<li><a href="#kicad-schematics">KiCad Schematics</a></li>
<li><a href="#dot-graphs">DOT Graphs</a></li>
</ul>
</li>
<li><a href="#converting-existing-designs-to-skidl">Converting Existing Designs to SKiDL</a></li>
<li><a href="#spice-simulations">SPICE Simulations</a></li>
</ul>
<h1 id="introduction">Introduction</h1>
<p>SKiDL is a module that allows you to compactly describe the interconnection of 
electronic circuits and components using Python.
The resulting Python program performs electrical rules checking
for common mistakes and outputs a netlist that serves as input to
a PCB layout tool.</p>
<p>First, let's look at a "normal" design flow in <a href="https://kicad.org">KiCad</a>:</p>
<p><img alt="Schematic-based PCB design flow" src="images/schematic-process-flow.png"></p>
<p>Here, you start off in a <em>schematic editor</em> (for KiCad, that's Eeschema) and
draw a schematic. From that, Eeschema generates
a <em>netlist file</em> that lists what components are used and how their pins are interconnected.
Then you'll use a <em>PCB layout tool</em> (like KiCad's PCBNEW) to arrange the part footprints
and draw the wire traces that connect the pins as specified in the netlist.
Once that is done, PCBNEW outputs a set of <em>Gerber files</em> that are sent to a
<em>PCB fabricator</em> who will create a physical PCB and ship it to you.
Then you'll post a picture of them on Twitter and promptly dump them
in a drawer for a few years because you got bored with the project.</p>
<p>In the SKiDL-based design flow, you use a <em>text editor</em> to create a <em>Python code file</em>
that employs the SKiDL library to describe interconnections of components.
This code file is executed by a <em>Python interpreter</em> and a netlist file is output.
From there, the design flow is identical to the schematic-based one
(including dumping the PCBs in a drawer).</p>
<p><img alt="Schematic-based PCB design flow" src="images/skidl-process-flow.png"></p>
<p>So, why would you <em>want</em> to use SKiDL?
Here are some of the features SKiDL brings to electronic design:</p>
<ul>
<li>Requires only a text editor and Python.</li>
<li>Has a powerful, flexible syntax (because it <em>is</em> Python).</li>
<li>Permits compact descriptions of electronic circuits (think about <em>not</em> tracing
  signals through a multi-page schematic).</li>
<li>Allows textual descriptions of electronic circuits (think about using 
  <code>diff</code> and <a href="https://en.wikipedia.org/wiki/Git">git</a> for circuits).</li>
<li>Performs electrical rules checking (ERC) for common mistakes (e.g., unconnected device I/O pins).</li>
<li>Supports linear / hierarchical / mixed descriptions of electronic designs.</li>
<li>Fosters design reuse (think about using <a href="pypi.org">PyPi</a> and <a href="github.com">Github</a>
  to distribute electronic designs).</li>
<li>Makes possible the creation of <em>smart circuit modules</em> whose behavior / structure are changed parametrically
  (think about filters whose component values are automatically adjusted based on your
  desired cutoff frequency).</li>
<li>Can work with any ECAD tool (for basic use, only two methods are needed: one for reading the part libraries and another
  for outputing the correct netlist format).</li>
<li>Takes advantage of all the benefits of the Python ecosystem (because it <em>is</em> Python).</li>
<li>Free software: MIT license.</li>
<li>Open source: <a href="https://github.com/devbisme/skidl">https://github.com/devbisme/skidl</a></li>
</ul>
<p>As a very simple example, the SKiDL program below describes a circuit that
takes an input voltage, divides it by three, and outputs it:</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>

<span class="c1"># Create input &amp; output voltages and ground reference.</span>
<span class="n">vin</span><span class="p">,</span> <span class="n">vout</span><span class="p">,</span> <span class="n">gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;VI&#39;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;VO&#39;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;GND&#39;</span><span class="p">)</span>

<span class="c1"># Create two resistors.</span>
<span class="n">r1</span><span class="p">,</span> <span class="n">r2</span> <span class="o">=</span> <span class="mi">2</span> <span class="o">*</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="s1">&#39;R&#39;</span><span class="p">,</span> <span class="n">TEMPLATE</span><span class="p">,</span> <span class="n">footprint</span><span class="o">=</span><span class="s1">&#39;Resistor_SMD.pretty:R_0805_2012Metric&#39;</span><span class="p">)</span>
<span class="n">r1</span><span class="o">.</span><span class="n">value</span> <span class="o">=</span> <span class="s1">&#39;1K&#39;</span>   <span class="c1"># Set upper resistor value.</span>
<span class="n">r2</span><span class="o">.</span><span class="n">value</span> <span class="o">=</span> <span class="s1">&#39;500&#39;</span>  <span class="c1"># Set lower resistor value.</span>

<span class="c1"># Connect the nets and resistors.</span>
<span class="n">vin</span> <span class="o">+=</span> <span class="n">r1</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span>      <span class="c1"># Connect the input to the upper resistor.</span>
<span class="n">gnd</span> <span class="o">+=</span> <span class="n">r2</span><span class="p">[</span><span class="mi">2</span><span class="p">]</span>      <span class="c1"># Connect the lower resistor to ground.</span>
<span class="n">vout</span> <span class="o">+=</span> <span class="n">r1</span><span class="p">[</span><span class="mi">2</span><span class="p">],</span> <span class="n">r2</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span> <span class="c1"># Output comes from the connection of the two resistors.</span>

<span class="c1"># Or you could do it with a single line of code:</span>
<span class="c1"># vin &amp;&amp; r1 &amp;&amp; vout &amp;&amp; r2 &amp;&amp; gnd</span>

<span class="c1"># Output the netlist to a file.</span>
<span class="n">generate_netlist</span><span class="p">(</span><span class="n">tool</span><span class="o">=</span><span class="n">KICAD9</span><span class="p">)</span>
</code></pre></div>

<p>And this is the netlist output that is passed to <code>PCBNEW</code> to
do the PCB layout:</p>
<div class="highlight"><pre><span></span><code>(export (version D)
  (design
    (source &quot;/media/devb/Main/devbisme/KiCad/tools/skidl/skidl/circuit.py&quot;)
    (date &quot;04/21/2021 10:43 AM&quot;)
    (tool &quot;SKiDL (0.0.31)&quot;))
  (components
    (comp (ref R1)
      (value 1K)
      (footprint Resistor_SMD.pretty:R_0805_2012Metric)
      (fields
        (field (name F0) R)
        (field (name F1) R))
      (libsource (lib Device) (part R))
      (sheetpath (names /top/15380172755090775681) (tstamps /top/15380172755090775681)))
    (comp (ref R2)
      (value 500)
      (footprint Resistor_SMD.pretty:R_0805_2012Metric)
      (fields
        (field (name F0) R)
        (field (name F1) R))
      (libsource (lib Device) (part R))
      (sheetpath (names /top/3019747424092552385) (tstamps /top/3019747424092552385))))
  (nets
    (net (code 1) (name GND)
      (node (ref R2) (pin 2)))
    (net (code 2) (name VI)
      (node (ref R1) (pin 1)))
    (net (code 3) (name VO)
      (node (ref R1) (pin 2))
      (node (ref R2) (pin 1))))
)
</code></pre></div>

<h1 id="installation">Installation</h1>
<p>SKiDL is pure Python so it's easy to install:</p>
<div class="highlight"><pre><span></span><code>$<span class="w"> </span>pip<span class="w"> </span>install<span class="w"> </span>skidl
</code></pre></div>

<p>While it's not entirely necessary, you may install some part libraries
for SKiDL to play with.
Some possible options are to do a full install of <a href="http://kicad.org/">KiCad</a> or
to install only the <a href="https://gitlab.com/kicad/libraries/kicad-symbols">KiCad libraries</a>.</p>
<p>Then, you'll need to set an environment variable so SKiDL can find the libraries.
For Windows, do this:</p>
<div class="highlight"><pre><span></span><code>set KICAD_SYMBOL_DIR=C:\Program Files\KiCad\share\kicad\kicad-symbols
</code></pre></div>

<p>And for linux-type OSes, define the environment variable in your <code>.bashrc</code> like so:</p>
<div class="highlight"><pre><span></span><code><span class="nb">export</span><span class="w"> </span><span class="nv">KICAD_SYMBOL_DIR</span><span class="o">=</span><span class="s2">&quot;/usr/share/kicad/library&quot;</span>
</code></pre></div>

<p><strong>These paths are OS-dependent</strong>, so launch KiCAD and click <code>Preferences-&gt;Configure Paths</code>
to reveal the needed paths.</p>
<h1 id="basic-usage">Basic Usage</h1>
<p>This is the minimum that you need to know to design electronic circuitry
using SKiDL:</p>
<ul>
<li>How to get access to SKiDL.</li>
<li>How to find and instantiate a component (or <em>part</em>).</li>
<li>How to connect <em>pins</em> of the parts to each other using <em>nets</em>.</li>
<li>How to run an ERC on the circuit.</li>
<li>How to generate a <em>netlist</em> for the circuit that serves as input to a PCB layout tool.</li>
</ul>
<p>I'll demonstrate these steps using SKiDL in an interactive Python session,
but normally the statements that are shown would be entered into a file and
executed as a Python script.</p>
<h2 id="accessing-skidl">Accessing SKiDL</h2>
<p>To use skidl in a project, just place the following at the top of your file:</p>
<div class="highlight"><pre><span></span><code><span class="kn">import</span> <span class="nn">skidl</span>
</code></pre></div>

<p>But for this tutorial, I'll just import everything:</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>
</code></pre></div>

<h2 id="finding-parts">Finding Parts</h2>
<h3 id="command-line-searching">Command-line Searching</h3>
<p>SKiDL provides the command-line utility <code>skidl-part-search</code> to search for parts.
It offers both one-shot searches and an interactive mode with part browsing capabilities.
For example, if you need an operational amplifier, then the following command would
pull up a long list of likely candidates:</p>
<div class="highlight"><pre><span></span><code>$<span class="w"> </span>skidl-part-search<span class="w"> </span>opamp
Found<span class="w"> </span><span class="m">419</span><span class="w"> </span>part<span class="o">(</span>s<span class="o">)</span><span class="w"> </span><span class="k">for</span>:<span class="w"> </span>opamp
Amplifier_Audio<span class="w"> </span><span class="p">|</span><span class="w"> </span>LM386<span class="w"> </span><span class="p">|</span><span class="w"> </span>Low<span class="w"> </span>Voltage<span class="w"> </span>Audio<span class="w"> </span>Power<span class="w"> </span>Amplifier,<span class="w"> </span>DIP-8/SOIC-8/SSOP-8
Amplifier_Audio<span class="w"> </span><span class="p">|</span><span class="w"> </span>OPA1622<span class="w"> </span><span class="p">|</span><span class="w"> </span>High-Fidelity,<span class="w"> </span>Bipolar-Input,<span class="w"> </span>Audio<span class="w"> </span>Operational<span class="w"> </span>Amplifier,<span class="w"> </span>VSON-10
Amplifier_Difference<span class="w"> </span><span class="p">|</span><span class="w"> </span>LM733CH<span class="w"> </span><span class="p">|</span><span class="w"> </span>Single<span class="w"> </span>Differential<span class="w"> </span>Amplifier,<span class="w"> </span>TO-5-10
Amplifier_Difference<span class="w"> </span><span class="p">|</span><span class="w"> </span>LM733CN<span class="w"> </span><span class="p">|</span><span class="w"> </span>Single<span class="w"> </span>Differential<span class="w"> </span>Amplifier,<span class="w"> </span>DIP-14
Amplifier_Difference<span class="w"> </span><span class="p">|</span><span class="w"> </span>LM733H<span class="w"> </span><span class="p">|</span><span class="w"> </span>Single<span class="w"> </span>Differential<span class="w"> </span>Amplifier,<span class="w"> </span>TO-5-10
Amplifier_Instrumentation<span class="w"> </span><span class="p">|</span><span class="w"> </span>INA128<span class="w"> </span><span class="p">|</span><span class="w"> </span>Precision,<span class="w"> </span>Low<span class="w"> </span>Power<span class="w"> </span>Instrumentation<span class="w"> </span>Amplifier<span class="w"> </span><span class="nv">G</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="m">1</span><span class="w"> </span>+<span class="w"> </span>50kOhm/Rg,<span class="w"> </span>DIP-8/SOIC-8...
</code></pre></div>

<p><code>skidl-part-search</code> accepts keywords and scans for them <em>anywhere</em> within the
name, description and keywords of all the parts in the library path.
(You can read more about how SKiDL handles libraries <a href="#libraries">here</a>.)
If you give it multiple terms, then it will find parts that contain <em>all</em>
those terms:</p>
<div class="highlight"><pre><span></span><code>$<span class="w"> </span>skidl-part-search<span class="w"> </span><span class="s1">&#39;opamp low-noise dip-8&#39;</span>
Found<span class="w"> </span><span class="m">7</span><span class="w"> </span>part<span class="o">(</span>s<span class="o">)</span><span class="w"> </span><span class="k">for</span>:<span class="w"> </span>opamp<span class="w"> </span>low-noise<span class="w"> </span>dip-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>NE5532<span class="w"> </span><span class="p">|</span><span class="w"> </span>Dual<span class="w"> </span>Low-Noise<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DIP-8/SOIC-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>NE5534<span class="w"> </span><span class="p">|</span><span class="w"> </span>Single<span class="w"> </span>Low-Noise<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DIP-8/SOIC-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>NJM5532<span class="w"> </span><span class="p">|</span><span class="w"> </span>Dual<span class="w"> </span>Low-Noise<span class="w"> </span>Operational<span class="w"> </span>Amplifier,<span class="w"> </span>DIP-8/DMP-8/SIP-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>SA5532<span class="w"> </span><span class="p">|</span><span class="w"> </span>Dual<span class="w"> </span>Low-Noise<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DIP-8/SOIC-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>SA5534<span class="w"> </span><span class="p">|</span><span class="w"> </span>Single<span class="w"> </span>Low-Noise<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DIP-8/SOIC-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>TL071<span class="w"> </span><span class="p">|</span><span class="w"> </span>Single<span class="w"> </span>Low-Noise<span class="w"> </span>JFET-Input<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DIP-8/SOIC-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>TL072<span class="w"> </span><span class="p">|</span><span class="w"> </span>Dual<span class="w"> </span>Low-Noise<span class="w"> </span>JFET-Input<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DIP-8/SOIC-8
</code></pre></div>

<p>You may also use the <code>|</code> character to find parts that contain at least one of a set
of choices:</p>
<div class="highlight"><pre><span></span><code>$<span class="w"> </span>skidl-part-search<span class="w"> </span><span class="s1">&#39;opamp (low-noise|dip-8)&#39;</span>
Found<span class="w"> </span><span class="m">118</span><span class="w"> </span>part<span class="o">(</span>s<span class="o">)</span><span class="w"> </span><span class="k">for</span>:<span class="w"> </span>opamp<span class="w"> </span><span class="o">(</span>low-noise<span class="p">|</span>dip-8<span class="o">)</span>
Amplifier_Audio<span class="w"> </span><span class="p">|</span><span class="w"> </span>LM386<span class="w"> </span><span class="p">|</span><span class="w"> </span>Low<span class="w"> </span>Voltage<span class="w"> </span>Audio<span class="w"> </span>Power<span class="w"> </span>Amplifier,<span class="w"> </span>DIP-8/SOIC-8/SSOP-8
Amplifier_Instrumentation<span class="w"> </span><span class="p">|</span><span class="w"> </span>INA128<span class="w"> </span><span class="p">|</span><span class="w"> </span>Precision,<span class="w"> </span>Low<span class="w"> </span>Power<span class="w"> </span>Instrumentation<span class="w"> </span>Amplifier<span class="w"> </span><span class="nv">G</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="m">1</span><span class="w"> </span>+<span class="w"> </span>50kOhm/Rg,<span class="w"> </span>DIP-8/SOIC-8
Amplifier_Instrumentation<span class="w"> </span><span class="p">|</span><span class="w"> </span>INA129<span class="w"> </span><span class="p">|</span><span class="w"> </span>Precision,<span class="w"> </span>Low<span class="w"> </span>Power<span class="w"> </span>Instrumentation<span class="w"> </span>Amplifier<span class="w"> </span><span class="nv">G</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="m">1</span><span class="w"> </span>+<span class="w"> </span><span class="m">49</span>.4kOhm/Rg,<span class="w"> </span>DIP-8/SOIC-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>AD797<span class="w"> </span><span class="p">|</span><span class="w"> </span>Ultralow<span class="w"> </span>Distortion,<span class="w"> </span>Ultralow<span class="w"> </span>Noise<span class="w"> </span>Op<span class="w"> </span>Amp,<span class="w"> </span>DIP-8/SOIC-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>AD8001AN<span class="w"> </span><span class="p">|</span><span class="w"> </span>Current<span class="w"> </span>Feedback<span class="w"> </span>Amplifier,<span class="w"> </span><span class="m">800</span><span class="w"> </span>MHz,<span class="w"> </span>50mW,<span class="w"> </span>DIP-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>AD817<span class="w"> </span><span class="p">|</span><span class="w"> </span>High<span class="w"> </span>Speed,<span class="w"> </span>Low<span class="w"> </span>Power<span class="w"> </span>Wide<span class="w"> </span>Supply<span class="w"> </span>Range<span class="w"> </span>Operational<span class="w"> </span>Amplifier,<span class="w"> </span>DIP-8/SOIC-8
...
</code></pre></div>

<p>If you need to search for a string containing spaces, just enclose it in quotes:</p>
<div class="highlight"><pre><span></span><code>$<span class="w"> </span>skidl-part-search<span class="w"> </span><span class="s1">&#39;opamp &quot;high performance&quot;&#39;</span>
Found<span class="w"> </span><span class="m">7</span><span class="w"> </span>part<span class="o">(</span>s<span class="o">)</span><span class="w"> </span><span class="k">for</span>:<span class="w"> </span>opamp<span class="w"> </span><span class="s2">&quot;high performance&quot;</span>
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>NJM2114<span class="w"> </span><span class="p">|</span><span class="w"> </span>Dual<span class="w"> </span>High<span class="w"> </span>Performance<span class="w"> </span>Low<span class="w"> </span>Noise<span class="w"> </span>Operational<span class="w"> </span>Amplifier,<span class="w"> </span>DIP-8/DMP-8/SIP-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>OPA134<span class="w"> </span><span class="p">|</span><span class="w"> </span>Single<span class="w"> </span>SoundPlus<span class="w"> </span>High<span class="w"> </span>Performance<span class="w"> </span>Audio<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DIP-8/SOIC-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>OPA1602<span class="w"> </span><span class="p">|</span><span class="w"> </span>Dual<span class="w"> </span>SoundPlus<span class="w"> </span>High<span class="w"> </span>Performance,<span class="w"> </span>Bipolar-Input<span class="w"> </span>Audio<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>SOIC-8/MSOP-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>OPA1604<span class="w"> </span><span class="p">|</span><span class="w"> </span>Quad<span class="w"> </span>SoundPlus<span class="w"> </span>High<span class="w"> </span>Performance,<span class="w"> </span>Bipolar-Input<span class="w"> </span>Audio<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>SOIC-14/TSSOP-14
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>OPA1612AxD<span class="w"> </span><span class="p">|</span><span class="w"> </span>Dual<span class="w"> </span>SoundPlus<span class="w"> </span>High<span class="w"> </span>Performance,<span class="w"> </span>Bipolar-Input<span class="w"> </span>Audio<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>SOIC-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>OPA2134<span class="w"> </span><span class="p">|</span><span class="w"> </span>Dual<span class="w"> </span>SoundPlus<span class="w"> </span>High<span class="w"> </span>Performance<span class="w"> </span>Audio<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DIP-8/SOIC-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>OPA4134<span class="w"> </span><span class="p">|</span><span class="w"> </span>Quad<span class="w"> </span>SoundPlus<span class="w"> </span>High<span class="w"> </span>Performance<span class="w"> </span>Audio<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>SOIC-14
</code></pre></div>

<h4 id="interactive-mode-with-part-browsing">Interactive Mode with Part Browsing</h4>
<p>For more detailed exploration, you can use the interactive mode that allows you to search multiple times
and browse through individual parts to see their pin details:</p>
<div class="highlight"><pre><span></span><code>$<span class="w"> </span>skidl-part-search<span class="w"> </span>--interactive
Interactive<span class="w"> </span>search<span class="w"> </span>mode.<span class="w"> </span>Use<span class="w"> </span>up/down<span class="w"> </span>arrows<span class="w"> </span><span class="k">for</span><span class="w"> </span>history.
Type<span class="w"> </span><span class="s1">&#39;quit&#39;</span>,<span class="w"> </span><span class="s1">&#39;exit&#39;</span>,<span class="w"> </span>or<span class="w"> </span><span class="s1">&#39;q&#39;</span><span class="w"> </span>to<span class="w"> </span>exit,<span class="w"> </span><span class="s1">&#39;browse&#39;</span><span class="w"> </span>to<span class="w"> </span>enter<span class="w"> </span>browse<span class="w"> </span>mode.

Search<span class="w"> </span>terms:<span class="w"> </span>lm358
Found<span class="w"> </span><span class="m">2</span><span class="w"> </span>part<span class="o">(</span>s<span class="o">)</span><span class="w"> </span><span class="k">for</span>:<span class="w"> </span>lm358
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>LM358<span class="w"> </span><span class="p">|</span><span class="w"> </span>Low-Power,<span class="w"> </span>Dual<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DIP-8/SOIC-8/TO-99-8
Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>LM358_DFN<span class="w"> </span><span class="p">|</span><span class="w"> </span>Low-Power,<span class="w"> </span>Dual<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DFN-8
Found<span class="w"> </span><span class="m">2</span><span class="w"> </span>part<span class="o">(</span>s<span class="o">)</span><span class="w"> </span><span class="k">for</span>:<span class="w"> </span>lm358
Type<span class="w"> </span><span class="s1">&#39;browse&#39;</span><span class="w"> </span>to<span class="w"> </span>navigate<span class="w"> </span>through<span class="w"> </span>results.

Search<span class="w"> </span>terms:<span class="w"> </span>browse
Browse<span class="w"> </span>mode:<span class="w"> </span><span class="m">2</span><span class="w"> </span>parts<span class="w"> </span>found.
Use<span class="w"> </span>UP/DOWN<span class="w"> </span>arrow<span class="w"> </span>keys<span class="w"> </span>to<span class="w"> </span>navigate,<span class="w"> </span>ENTER<span class="w"> </span>to<span class="w"> </span>show<span class="w"> </span>details,<span class="w"> </span><span class="s1">&#39;s&#39;</span><span class="w"> </span><span class="k">for</span><span class="w"> </span>search<span class="w"> </span>mode,<span class="w"> </span><span class="s1">&#39;q&#39;</span><span class="w"> </span>to<span class="w"> </span>quit.

<span class="o">[</span><span class="m">1</span>/2<span class="o">]</span><span class="w"> </span>Amplifier_Operational<span class="w"> </span><span class="p">|</span><span class="w"> </span>LM358<span class="w"> </span><span class="p">|</span><span class="w"> </span>Low-Power,<span class="w"> </span>Dual<span class="w"> </span>Operational<span class="w"> </span>Amplifiers,<span class="w"> </span>DIP-8/SOIC-8/TO-99-8<span class="w"> </span><span class="o">(</span>ENTER/UP/DOWN/s/q<span class="o">)</span>
</code></pre></div>

<p>In browse mode, you can:
- Use <strong>UP/DOWN arrow keys</strong> to navigate through the search results
- Press <strong>ENTER</strong> to display detailed information about the selected part, including all its pins
- Type <strong>'s'</strong> to return to search mode
- Type <strong>'q'</strong> to quit</p>
<p>When you press ENTER on a part, you'll see detailed pin information:</p>
<div class="highlight"><pre><span></span><code>Showing details for: LM358 from Amplifier_Operational
------------------------------------------------------------
Part: LM358
Library: Amplifier_Operational
Description: Low-Power, Dual Operational Amplifiers, DIP-8/SOIC-8/TO-99-8
Aliases: LM358
Keywords: dual opamp

Pins:
┏━━━━━━┳━━━━━━━┳━━━━━━━━┓
┃ Pin# ┃ Names ┃ Type   ┃
┡━━━━━━╇━━━━━━━╇━━━━━━━━┩
│ 1    │ p1,~  │ OUTPUT │
│ 2    │ -,p2  │ INPUT  │
│ 3    │ +,p3  │ INPUT  │
│ 4    │ p4,V- │ PWRIN  │
│ 5    │ +,p5  │ INPUT  │
│ 6    │ -,p6  │ INPUT  │
│ 7    │ p7,~  │ OUTPUT │
│ 8    │ p8,V+ │ PWRIN  │
└──────┴───────┴────────┘
------------------------------------------------------------

[1/2] Amplifier_Operational | LM358 | Low-Power, Dual Operational Amplifiers, DIP-8/SOIC-8/TO-99-8 (ENTER/UP/DOWN/s/q)
</code></pre></div>

<h4 id="output-formatting-and-options">Output Formatting and Options</h4>
<p>The search utility supports various output formats and options:</p>
<div class="highlight"><pre><span></span><code><span class="c1"># Display results in a table format (requires rich module)</span>
<span class="o">$</span><span class="w"> </span><span class="n">skidl</span><span class="o">-</span><span class="n">part</span><span class="o">-</span><span class="n">search</span><span class="w"> </span><span class="o">--</span><span class="n">table</span><span class="w"> </span><span class="n">opamp</span>

<span class="c1"># Limit the number of results</span>
<span class="o">$</span><span class="w"> </span><span class="n">skidl</span><span class="o">-</span><span class="n">part</span><span class="o">-</span><span class="n">search</span><span class="w"> </span><span class="o">--</span><span class="n">limit</span><span class="w"> </span><span class="mi">10</span><span class="w"> </span><span class="n">opamp</span>

<span class="c1"># Search specific ECAD tool libraries</span>
<span class="o">$</span><span class="w"> </span><span class="n">skidl</span><span class="o">-</span><span class="n">part</span><span class="o">-</span><span class="n">search</span><span class="w"> </span><span class="o">--</span><span class="k">tool</span><span class="w"> </span><span class="n">kicad7</span><span class="w"> </span><span class="n">opamp</span>

<span class="c1"># Custom output formatting</span>
<span class="o">$</span><span class="w"> </span><span class="n">skidl</span><span class="o">-</span><span class="n">part</span><span class="o">-</span><span class="n">search</span><span class="w"> </span><span class="o">--</span><span class="n">format</span><span class="w"> </span><span class="s2">&quot;{part_name} from {lib_name}&quot;</span><span class="w"> </span><span class="n">opamp</span>

<span class="c1"># Save results to a file</span>
<span class="o">$</span><span class="w"> </span><span class="n">skidl</span><span class="o">-</span><span class="n">part</span><span class="o">-</span><span class="n">search</span><span class="w"> </span><span class="o">--</span><span class="n">output</span><span class="w"> </span><span class="n">results</span><span class="o">.</span><span class="n">txt</span><span class="w"> </span><span class="n">opamp</span>
</code></pre></div>

<p>In addition to searching for parts, you may also search for footprints using the
<code>search_footprints</code> command. It works similarly to the <code>search</code> command:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; search_footprints(&#39;QFN-48&#39;)

Package_DFN_QFN: QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm (&quot;QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_noLead_generator.py&quot; - &quot;QFN NoLead&quot;)
Package_DFN_QFN: QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm_ThermalVias (&quot;QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_noLead_generator.py&quot; - &quot;QFN NoLead&quot;)
Package_DFN_QFN: QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm (&quot;QFN, 48 Pin (https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1p5.pdf#page=20), generated with kicad-footprint-generator ipc_noLead_generator.py&quot; - &quot;QFN NoLead&quot;)
Package_DFN_QFN: QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm_ThermalVias (&quot;QFN, 48 Pin (https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1p5.pdf#page=20), generated with kicad-footprint-generator ipc_noLead_generator.py&quot; - &quot;QFN NoLead&quot;)
...
</code></pre></div>

<h3 id="zyc-a-gui-search-tool">Zyc: A GUI Search Tool</h3>
<p>If you want to avoid using command-line tools,
<a href="https://devbisme.github.io/zyc"><code>zyc</code></a> lets you search for parts and footprints using a GUI.
You can read more about it <a href="https://devbisme.github.io/skidl/docs/_site/blog/worst-part-of-skidl">here</a>.</p>
<h2 id="instantiating-parts">Instantiating Parts</h2>
<p>You instantiate a part using its name and the library that contains it:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; resistor = Part(&#39;Device&#39;,&#39;R&#39;)
</code></pre></div>

<p>You may customize the resistor by setting its <code>value</code> attribute:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; resistor.value = &#39;1K&#39; 
&gt;&gt;&gt; resistor.value        
&#39;1K&#39;                      
</code></pre></div>

<p>It's also possible to set attributes when creating a part:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; resistor = Part(&#39;Device&#39;, &#39;R&#39;, value=&#39;2K&#39;)
&gt;&gt;&gt; resistor.value
&#39;2K&#39;
</code></pre></div>

<p>The <code>ref</code> attribute holds the part <em>reference</em>. It's set automatically
when you create the part:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; resistor.ref
&#39;R1&#39;
</code></pre></div>

<p>Since this was the first resistor we created, it has the honor of being named <code>R1</code>.
But you can easily change that:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; resistor.ref = &#39;R5&#39;
&gt;&gt;&gt; resistor.ref
&#39;R5&#39;
</code></pre></div>

<p>If we create another resistor, it will be assigned another
reference that's distinct from any existing references:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; another_res = Part(&#39;Device&#39;,&#39;R&#39;)   
&gt;&gt;&gt; another_res.ref                        
&#39;R2&#39;
</code></pre></div>

<p>What if we tried renaming the first resistor to <code>R2</code>?</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; resistor.ref = &#39;R2&#39;
&gt;&gt;&gt; resistor.ref
&#39;R2_1&#39;
</code></pre></div>

<p>Since the <code>R2</code> reference was already taken, SKiDL tried to give us
something close to what we wanted.
SKiDL won't let parts of the same type have exactly the same reference.</p>
<p>The <code>ref</code>, <code>value</code>, and <code>footprint</code> attributes are necessary when generating
a final netlist for your circuit.
Since a part is stored in a Python object, you may add any
other attributes you want using <code>setattr()</code>.
But if you want those attributes to be passed on within the netlist, then you
should probably add them as <a href="#part-fields">part fields</a>.</p>
<h2 id="connecting-pins">Connecting Pins</h2>
<p>Parts are great, but not very useful if they aren't connected to anything.
The connections between parts are called <em>nets</em> (think of them as wires)
and every net has one or more part <em>pins</em> attached to it.
SKiDL makes it easy to create nets and connect pins to them. 
To demonstrate, let's build the voltage divider circuit
shown in the introduction.</p>
<p>First, start by creating two resistors (note that I've also added the
<code>footprint</code> attribute that describes the physical package for the resistors):</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span> <span class="n">rup</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="s1">&#39;R&#39;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s1">&#39;1K&#39;</span><span class="p">,</span> <span class="n">footprint</span><span class="o">=</span><span class="s1">&#39;Resistor_SMD.pretty:R_0805_2012Metric&#39;</span><span class="p">)</span>                            
<span class="o">&gt;&gt;&gt;</span> <span class="n">rlow</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="s1">&#39;R&#39;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s1">&#39;500&#39;</span><span class="p">,</span> <span class="n">footprint</span><span class="o">=</span><span class="s1">&#39;Resistor_SMD.pretty:R_0805_2012Metric&#39;</span><span class="p">)</span>                          
<span class="o">&gt;&gt;&gt;</span> <span class="n">rup</span><span class="o">.</span><span class="n">ref</span><span class="p">,</span> <span class="n">rlow</span><span class="o">.</span><span class="n">ref</span>                                                
<span class="p">(</span><span class="s1">&#39;R1&#39;</span><span class="p">,</span> <span class="s1">&#39;R2&#39;</span><span class="p">)</span>                                                         
<span class="o">&gt;&gt;&gt;</span> <span class="n">rup</span><span class="o">.</span><span class="n">value</span><span class="p">,</span> <span class="n">rlow</span><span class="o">.</span><span class="n">value</span>                                            
<span class="p">(</span><span class="s1">&#39;1K&#39;</span><span class="p">,</span> <span class="s1">&#39;500&#39;</span><span class="p">)</span>     
</code></pre></div>

<p>To bring the voltage that will be divided into the circuit, let's create a net:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; v_in = Net(&#39;VIN&#39;)
&gt;&gt;&gt; v_in.name
&#39;VIN&#39;
</code></pre></div>

<p>Now attach the net to one of the pins of the <code>rup</code> resistor
(resistors are bidirectional which means it doesn't matter which pin, so pick pin 1):</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; rup[1] += v_in
</code></pre></div>

<p>You can verify that the net is attached to pin 1 of the resistor like this:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; rup[1].net
VIN: Pin R1/1/~/PASSIVE
</code></pre></div>

<p>Next, create a ground reference net and attach it to <code>rlow</code>:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; gnd = Net(&#39;GND&#39;)
&gt;&gt;&gt; rlow[1] += gnd
&gt;&gt;&gt; rlow[1].net
GND: Pin R2/1/~/PASSIVE
</code></pre></div>

<p>Finally, the divided voltage has to come out of the circuit on a net.
This can be done in several ways.
The first way is to define the output net and then attach the unconnected
pins of both resistors to it:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; v_out = Net(&#39;VO&#39;)
&gt;&gt;&gt; v_out += rup[2], rlow[2]
&gt;&gt;&gt; rup[2].net, rlow[2].net
(VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE, VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE)
</code></pre></div>

<p>An alternate method is to connect the resistors and then attach their
junction to the output net:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; rup[2] += rlow[2]
&gt;&gt;&gt; v_out = Net(&#39;VO&#39;)
&gt;&gt;&gt; v_out += rlow[2]
&gt;&gt;&gt; rup[2].net, rlow[2].net
(VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE, VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE)
</code></pre></div>

<p>Either way works! Sometimes pin-to-pin connections are easier when you're
just wiring two devices together, while the pin-to-net connection method
excels when three or more pins have a common connection.</p>
<p>With more complicated parts, the code is often clearer if you use pin names instead
of numbers. Check out <a href="#accessing-part-pins">this section</a> for how to do that.</p>
<h2 id="checking-for-errors">Checking for Errors</h2>
<p>Once the parts are wired together, you may do simple electrical rules checking
like this:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; ERC()                           

2 warnings found during ERC.        
0 errors found during ERC.          
</code></pre></div>

<p>Since this is an interactive session, the ERC warnings and errors are stored 
in the file <code>skidl.erc</code>. (Normally, your SKiDL circuit description is stored
as a Python script such as <code>my_circuit.py</code> and the <code>ERC()</code> function will
dump its messages to <code>my_circuit.erc</code>.)
The ERC messages are:</p>
<div class="highlight"><pre><span></span><code><span class="n">WARNING</span><span class="o">:</span><span class="w"> </span><span class="n">Only</span><span class="w"> </span><span class="n">one</span><span class="w"> </span><span class="n">pin</span><span class="w"> </span><span class="o">(</span><span class="n">PASSIVE</span><span class="w"> </span><span class="n">pin</span><span class="w"> </span><span class="mi">1</span><span class="sr">/~ of R/</span><span class="n">R1</span><span class="o">)</span><span class="w"> </span><span class="n">attached</span><span class="w"> </span><span class="n">to</span><span class="w"> </span><span class="n">net</span><span class="w"> </span><span class="n">VIN</span><span class="o">.</span>
<span class="n">WARNING</span><span class="o">:</span><span class="w"> </span><span class="n">Only</span><span class="w"> </span><span class="n">one</span><span class="w"> </span><span class="n">pin</span><span class="w"> </span><span class="o">(</span><span class="n">PASSIVE</span><span class="w"> </span><span class="n">pin</span><span class="w"> </span><span class="mi">1</span><span class="sr">/~ of R/</span><span class="n">R2</span><span class="o">)</span><span class="w"> </span><span class="n">attached</span><span class="w"> </span><span class="n">to</span><span class="w"> </span><span class="n">net</span><span class="w"> </span><span class="n">GND</span><span class="o">.</span>
</code></pre></div>

<p>These messages are generated because the <code>VIN</code> and <code>GND</code> nets each have only
a single pin on them and this usually indicates a problem.
But it's OK for this simple example, so the ERC can be turned off for
these two nets to prevent the spurious messages:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; v_in.do_erc = False
&gt;&gt;&gt; gnd.do_erc = False
&gt;&gt;&gt; ERC()

No ERC errors or warnings found.
</code></pre></div>

<h2 id="generating-a-netlist-or-pcb">Generating a Netlist or PCB</h2>
<p>The end goal of using SKiDL is to generate a netlist that can be used
with a layout tool to generate a PCB. The netlist is output as follows:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; generate_netlist()
</code></pre></div>

<p>Like the ERC output, the netlist shown below is stored in the file <code>skidl.net</code>.
But if your SKiDL circuit description is in the <code>my_circuit.py</code> file, 
then the netlist will be stored in <code>my_circuit.net</code>.</p>
<div class="highlight"><pre><span></span><code>(export (version D)
  (design
    (source &quot;/media/devb/Main/devbisme/KiCad/tools/skidl/skidl/circuit.py&quot;)
    (date &quot;04/22/2021 01:50 PM&quot;)
    (tool &quot;SKiDL (0.0.31dev)&quot;))
  (components
    (comp (ref R1)
      (value 1K)
      (footprint Resistor_SMD.pretty:R_0805_2012Metric)
      (fields
        (field (name F0) R)
        (field (name F1) R))
      (libsource (lib Device) (part R))
      (sheetpath (names /top/16316864629425674383) (tstamps /top/16316864629425674383)))
    (comp (ref R2)
      (value 500)
      (footprint Resistor_SMD.pretty:R_0805_2012Metric)
      (fields
        (field (name F0) R)
        (field (name F1) R))
      (libsource (lib Device) (part R))
      (sheetpath (names /top/8136002053123588309) (tstamps /top/8136002053123588309))))
  (nets
    (net (code 1) (name GND)
      (node (ref R2) (pin 1)))
    (net (code 2) (name VIN)
      (node (ref R1) (pin 1)))
    (net (code 3) (name VO)
      (node (ref R1) (pin 2))
      (node (ref R2) (pin 2))))
)
</code></pre></div>

<p>You can also generate the netlist in XML format:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; generate_xml()
</code></pre></div>

<p>This is useful in a KiCad environment where the XML file is used as the
input to BOM-generation tools.</p>
<p>If you're designing with KiCad and want to skip some steps, you may go 
directly to a PCB like this:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; generate_pcb()
</code></pre></div>

<p>This outputs a <code>.kicad_pcb</code> file that you can open in PCBNEW without
having to import the netlist.
(Note that you will need to have KiCad installed since <code>generate_pcb</code> uses its 
<code>pcbnew</code> Python library to create the PCB.)</p>
<p>The <code>generate_pcb()</code> function accepts the following optional arguments:</p>
<ul>
<li><code>pcb_file</code>: Either a file object that can be written to, or a string containing a file name, or <code>None</code>.</li>
<li><code>fp_libs</code>: List of paths to directories containing footprint libraries.</li>
</ul>
<h1 id="going-deeper">Going Deeper</h1>
<p>This section will talk about more advanced SKiDL features
that make designing complicated circuits easier.</p>
<h2 id="basic-skidl-objects-parts-pins-nets-buses">Basic SKiDL Objects: Parts, Pins, Nets, Buses</h2>
<p>SKiDL uses four types of objects to represent a circuit: <code>Part</code>, <code>Pin</code>,
<code>Net</code>, and <code>Bus</code>.</p>
<p>The <code>Part</code> object represents an electronic component, which SKiDL thinks of as a simple
bag of <code>Pin</code> objects with a few other attributes attached 
(like the part number, name, reference, value, footprint, etc.).</p>
<p>The <code>Pin</code> object represents a terminal that brings an electronic signal into
and out of the part. Each <code>Pin</code> object stores information on which part it belongs to
and which nets it is attached to.</p>
<p>A <code>Net</code> object is kind of like a <code>Part</code>: it's a simple bag of pins.
But unlike a part, pins can be added to a net when a pin on some part is attached
or when it is merged with another net.</p>
<p>Finally, a <code>Bus</code> is just a collection of multiple <code>Net</code> objects.
A bus of a certain width can be created from a number of existing nets,
newly-created nets, or both.</p>
<h2 id="creating-skidl-objects">Creating SKiDL Objects</h2>
<p>Here's the most common way to create a part in your circuit:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_part</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;some_library&#39;</span><span class="p">,</span> <span class="s1">&#39;some_part_name&#39;</span><span class="p">)</span>
</code></pre></div>

<p>When this is processed, the current directory will be checked for a file
called <code>some_library.lib</code> or <code>some_library.kicad_sym</code>
which will be opened and scanned for a part with the
name <code>some_part_name</code>. If the file is not found or it doesn't contain
the requested part, then the process will be repeated using KiCad's default
library directory.
(You may change SKiDL's library search by changing the list of directories
stored in the <code>skidl.lib_search_paths_kicad</code> list.)</p>
<p>You're not restricted to using only the current directory or the KiCad default
directory to search for parts. You can also search any file for a part by 
using a full file name:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_part</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;C:/my_libs/my_great_parts.lib&#39;</span><span class="p">,</span> <span class="s1">&#39;my_super_regulator&#39;</span><span class="p">)</span>
</code></pre></div>

<p>You're also not restricted to getting an exact match on the part name: you may
use a <em>regular expression</em> instead. For example, this will find a part
with "358" anywhere in a part name or alias:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_part</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Amplifier_Audio&#39;</span><span class="p">,</span> <span class="s1">&#39;.*386.*&#39;</span><span class="p">)</span>
</code></pre></div>

<p>If the regular expression matches more than one part, then you'll only get the
first match and a warning that multiple parts were found.</p>
<p>Once you have the part, you can <a href="#instantiating-parts">set its attributes</a>
as was described previously.</p>
<p>Creating nets and buses is straightforward:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>               <span class="c1"># An unnamed net.</span>
<span class="n">my_other_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;Fred&#39;</span><span class="p">)</span>   <span class="c1"># A named net.</span>
<span class="n">my_bus</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">&#39;bus_name&#39;</span><span class="p">,</span> <span class="mi">8</span><span class="p">)</span>  <span class="c1"># Named, byte-wide bus with nets bus_name0, bus_name1, ...</span>
<span class="n">anon_bus</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="mi">4</span><span class="p">)</span>            <span class="c1"># Four-bit bus with an automatically-assigned name.</span>
</code></pre></div>

<p>As with parts, SKiDL will alter the name you assign if it collides with another net or bus
having the same name.</p>
<p>You may also create a bus by combining existing nets, buses, or the pins of parts
in any combination:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_part</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Amplifier_Audio&#39;</span><span class="p">,</span> <span class="s1">&#39;LM386&#39;</span><span class="p">)</span>
<span class="n">a_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>
<span class="n">b_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>
<span class="n">bus_nets</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">&#39;net_bus&#39;</span><span class="p">,</span> <span class="n">a_net</span><span class="p">,</span> <span class="n">b_net</span><span class="p">)</span>            <span class="c1"># A 2-bit bus from nets.</span>
<span class="n">bus_pins</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">&#39;pin_bus&#39;</span><span class="p">,</span> <span class="n">my_part</span><span class="p">[</span><span class="mi">1</span><span class="p">],</span> <span class="n">my_part</span><span class="p">[</span><span class="mi">3</span><span class="p">])</span>  <span class="c1"># A 2-bit bus from pins.</span>
<span class="n">bus_buses</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">&#39;bus_bus&#39;</span><span class="p">,</span> <span class="n">my_bus</span><span class="p">)</span>                 <span class="c1"># An 8-bit bus.</span>
<span class="n">bus_combo</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">&#39;mongrel&#39;</span><span class="p">,</span> <span class="mi">8</span><span class="p">,</span> <span class="n">a_net</span><span class="p">,</span> <span class="n">my_bus</span><span class="p">,</span> <span class="n">my_part</span><span class="p">[</span><span class="mi">2</span><span class="p">])</span>  <span class="c1"># 8+1+8+1 = 18-bit bus.</span>
</code></pre></div>

<p>You can also build a bus incrementally by inserting or extending it with
widths, nets, buses or pins:</p>
<div class="highlight"><pre><span></span><code><span class="n">bus</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">&#39;A&#39;</span><span class="p">,</span> <span class="mi">8</span><span class="p">)</span>   <span class="c1"># Eight-bit bus.</span>
<span class="n">bus</span><span class="o">.</span><span class="n">insert</span><span class="p">(</span><span class="mi">4</span><span class="p">,</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">&#39;I&#39;</span><span class="p">,</span> <span class="mi">3</span><span class="p">))</span>  <span class="c1"># Insert 3-bit bus before bus line bus[4].</span>
<span class="n">bus</span><span class="o">.</span><span class="n">extend</span><span class="p">(</span><span class="mi">5</span><span class="p">,</span> <span class="n">Pin</span><span class="p">(),</span> <span class="n">Net</span><span class="p">())</span> <span class="c1"># Extend bus with another 5-bit bus, a pin, and a net.</span>
</code></pre></div>

<p>And finally, you may create a <code>Pin</code> object although you'll probably never do this
unless you're building a <code>Part</code> object from scratch:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; p = Pin(num=1, name=&#39;my_pin&#39;, func=Pin.TRISTATE)
&gt;&gt;&gt; p
Pin ???/1/my_pin/TRISTATE
</code></pre></div>

<h2 id="finding-skidl-objects">Finding SKiDL Objects</h2>
<p>If you want to access a bus, net, or part that's already been created,
use the <code>get()</code> class method:</p>
<div class="highlight"><pre><span></span><code><span class="n">n</span> <span class="o">=</span> <span class="n">Net</span><span class="o">.</span><span class="n">get</span><span class="p">(</span><span class="s1">&#39;Fred&#39;</span><span class="p">)</span>  <span class="c1"># Find the existing Net object named &#39;Fred&#39;.</span>
<span class="n">b</span> <span class="o">=</span> <span class="n">Bus</span><span class="o">.</span><span class="n">get</span><span class="p">(</span><span class="s1">&#39;A&#39;</span><span class="p">)</span>     <span class="c1"># Find the existing Bus object named &#39;A&#39;.</span>
<span class="n">p</span> <span class="o">=</span> <span class="n">Part</span><span class="o">.</span><span class="n">get</span><span class="p">(</span><span class="s1">&#39;AS6C1616&#39;</span><span class="p">)</span>  <span class="c1"># Find all parts with this part name.</span>
</code></pre></div>

<p>If a net or bus with the exact name is found (no wild-card searches using regular expressions are allowed),
then that SKiDL object is returned.
Otherwise, <code>None</code> is returned.</p>
<p>For parts, the search is performed using string matching on part names,
references (e.g., <code>R4</code>), and aliases.
In addition, regular expression matching is used to search within the
part descriptions, so you could search for all parts with "ram" in their description.</p>
<p>If you want to access a particular bus or net and
create it if it doesn't already exist, then use the <code>fetch()</code> class method:</p>
<div class="highlight"><pre><span></span><code><span class="n">n</span> <span class="o">=</span> <span class="n">Net</span><span class="o">.</span><span class="n">fetch</span><span class="p">(</span><span class="s1">&#39;Fred&#39;</span><span class="p">)</span>  <span class="c1"># Find the existing Net object named &#39;Fred&#39; or create it if not found.</span>
<span class="n">b</span> <span class="o">=</span> <span class="n">Bus</span><span class="o">.</span><span class="n">fetch</span><span class="p">(</span><span class="s1">&#39;A&#39;</span><span class="p">,</span> <span class="mi">8</span><span class="p">)</span>  <span class="c1"># Find the existing Bus object named &#39;A&#39; or create it if not found.</span>
</code></pre></div>

<p>Note that with the <code>Bus.fetch()</code> method, you also have to provide the arguments to
build the bus (such as its width) in case it doesn't exist.</p>
<h2 id="copying-skidl-objects">Copying SKiDL Objects</h2>
<p>Instead of creating a SKiDL object from scratch, sometimes it's easier to just
copy an existing object. Here are some examples of creating a resistor and then making
some copies of it:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; r1 = Part(&#39;Device&#39;, &#39;R&#39;, value=500)    # Add a resistor to the circuit.
&gt;&gt;&gt; r2 = r1.copy()                         # Make a single copy of the resistor.
&gt;&gt;&gt; r2_lst = r1.copy(1)                    # Make a single copy, but return it in a list.
&gt;&gt;&gt; r3 = r1.copy(value=&#39;1K&#39;)               # Make a single copy, but give it a different value.
&gt;&gt;&gt; r4 = r1(value=&#39;1K&#39;)                    # You can also call the object directly to make copies.
&gt;&gt;&gt; r5, r6, r7 = r1(3, value=&#39;1K&#39;)         # Make three copies of a 1-KOhm resistor.
&gt;&gt;&gt; r8, r9, r10 = r1(value=[110,220,330])  # Make three copies, each with a different value.
&gt;&gt;&gt; r11, r12 = 2 <span class="gs">* r1                      # Make copies using the &#39;*</span>&#39; operator.
&gt;&gt;&gt; r13, r14 = 2 * r1(value=&#39;1K&#39;)          # This actually makes three 1-KOhm resistors!!!
</code></pre></div>

<p>The last example demonstrates an unexpected result when using the <code>*</code> operator:</p>
<ol>
<li>The resistor is called with a value of 1-KOhm, creating a copy of the resistor with that value of resistance.</li>
<li>The <code>*</code> operator is applied to the resistor <em>copy</em>, returning two more 1-KOhm resistors. Now the original resistor has been copied <em>three</em> times.</li>
<li>The two new resistors returned by the <code>*</code> operator are assigned to <code>r13</code> and <code>r14</code>.</li>
</ol>
<p>After these operations, the second and third copies can be referenced, but any reference to
the first copy has been lost so it just floats around, unconnected to anything, only to raise
errors later when the ERC is run.</p>
<p>In some cases it's clearer to create parts by copying a <em>template part</em> that
doesn't actually get included in the netlist for the circuitry:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">rt</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nv">Part</span><span class="ss">(</span><span class="s1">&#39;Device&#39;</span>,<span class="w"> </span><span class="s1">&#39;R&#39;</span>,<span class="w"> </span><span class="nv">dest</span><span class="o">=</span><span class="nv">TEMPLATE</span><span class="ss">)</span><span class="w">  </span>#<span class="w"> </span><span class="nv">Create</span><span class="w"> </span><span class="nv">a</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">just</span><span class="w"> </span><span class="k">for</span><span class="w"> </span><span class="nv">copying</span>.<span class="w"> </span><span class="nv">It</span><span class="err">&#39;s not added to the circuit.</span>
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">r1</span>,<span class="w"> </span><span class="nv">r2</span>,<span class="w"> </span><span class="nv">r3</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nv">rt</span><span class="ss">(</span><span class="mi">3</span>,<span class="w"> </span><span class="nv">value</span><span class="o">=</span><span class="s1">&#39;1K&#39;</span><span class="ss">)</span><span class="w">           </span>#<span class="w"> </span><span class="nv">Make</span><span class="w"> </span><span class="nv">three</span><span class="w"> </span><span class="mi">1</span><span class="o">-</span><span class="nv">KOhm</span><span class="w"> </span><span class="nv">copies</span><span class="w"> </span><span class="nv">that</span><span class="w"> </span><span class="nv">become</span><span class="w"> </span><span class="nv">part</span><span class="w"> </span><span class="nv">of</span><span class="w"> </span><span class="nv">the</span><span class="w"> </span><span class="nv">actual</span><span class="w"> </span><span class="nv">circuitry</span>.
</code></pre></div>

<h2 id="accessing-part-pins-and-bus-lines">Accessing Part Pins and Bus Lines</h2>
<h3 id="accessing-part-pins">Accessing Part Pins</h3>
<p>You may access the pins on a part or the individual nets of a bus
using numbers, slices, strings, and regular expressions, either singly or in any combination.</p>
<p>Suppose you have a PIC10 processor in a six-pin package:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;)
&gt;&gt;&gt; pic10

 PIC10F220-IOT (PIC10F222-IOT): 512W Flash, 24B SRAM, SOT-23-6
    Pin U3/1/GP0/BIDIRECTIONAL
    Pin U3/2/VSS/POWER-IN
    Pin U3/3/GP1/BIDIRECTIONAL
    Pin U3/4/GP2/BIDIRECTIONAL
    Pin U3/5/VDD/POWER-IN
    Pin U3/6/GP3/INPUT
</code></pre></div>

<p>The most natural way to access one of its pins is to give the pin number
in brackets:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10[3]
Pin U1/3/GP1/BIDIRECTIONAL
</code></pre></div>

<p>(If you have a part in a BGA package with pins numbers like <code>C11</code>, then
you'll have to enter the pin number as a quoted string like <code>'C11'</code>.)</p>
<p>You can also get several pins at once in a list:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10[3,1,6]
[Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/1/GP0/BIDIRECTIONAL, Pin U1/6/GP3/INPUT]
</code></pre></div>

<p>You can even use Python slice notation:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10[2:4]  # Get pins 2 through 4.
[Pin U1/2/VSS/POWER-IN, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/4/GP2/BIDIRECTIONAL]
&gt;&gt;&gt; pic10[4:2]  # Get pins 4 through 2.
[Pin U1/4/GP2/BIDIRECTIONAL, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/2/VSS/POWER-IN]
&gt;&gt;&gt; pic10[:]    # Get all the pins.
[Pin U1/1/GP0/BIDIRECTIONAL,
 Pin U1/2/VSS/POWER-IN,
 Pin U1/3/GP1/BIDIRECTIONAL,
 Pin U1/4/GP2/BIDIRECTIONAL,
 Pin U1/5/VDD/POWER-IN,
 Pin U1/6/GP3/INPUT]
</code></pre></div>

<p>(It's important to note that the slice notation used by SKiDL for parts is slightly
different than standard Python. In Python, a slice <code>n:m</code> would fetch indices
<code>n</code>, <code>n+1</code>, <code>...</code>, <code>m-1</code>. With SKiDL, it actually fetches all the
way up to the last number: <code>n</code>, <code>n+1</code>, <code>...</code>, <code>m-1</code>, <code>m</code>.
The reason for doing this is that most electronics designers are used to
the bounds on a slice including both endpoints. Perhaps it is a mistake to
do it this way. We'll see...)</p>
<p>In addition to the bracket notation, you may also get a single pin using an attribute name
that begins with a '<code>p</code>' followed by the pin number:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10.p2
Pin U1/2/VSS/POWER-IN
</code></pre></div>

<p>Instead of pin numbers, sometimes it makes the design intent more clear to 
access pins by their names.
For example, it's more obvious that a voltage supply net is being
attached to the power pin of the processor when it's expressed like this:</p>
<div class="highlight"><pre><span></span><code><span class="n">pic10</span><span class="p">[</span><span class="s1">&#39;VDD&#39;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;supply_5V&#39;</span><span class="p">)</span>
</code></pre></div>

<p>If a pin name contains spaces, then enclose the name within nested quotes:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span> <span class="n">pic10</span><span class="p">[</span><span class="s1">&#39;GP1&#39;</span><span class="p">]</span><span class="o">.</span><span class="n">aliases</span> <span class="o">+=</span> <span class="s1">&#39;name with spaces&#39;</span>
<span class="o">&gt;&gt;&gt;</span> <span class="n">pic10</span><span class="p">[</span><span class="s1">&#39;&quot;name with spaces&quot;&#39;</span><span class="p">]</span>
<span class="n">Pin</span> <span class="n">U2</span><span class="o">/</span><span class="mi">3</span><span class="o">/</span><span class="n">GP1</span><span class="p">,</span><span class="n">GP1</span><span class="p">,</span><span class="n">name</span> <span class="k">with</span> <span class="n">spaces</span><span class="p">,</span><span class="n">p3</span><span class="o">/</span><span class="n">BIDIRECTIONAL</span>
</code></pre></div>

<p>Like pin numbers, pin names can also be used as attributes to access the pin:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10.VDD
Pin U1/5/VDD/POWER-IN
</code></pre></div>

<p>You can use multiple names to get more than one pin:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10[&#39;VDD&#39;,&#39;VSS&#39;]
[Pin U1/5/VDD/POWER-IN, Pin U1/2/VSS/POWER-IN]
</code></pre></div>

<p>It can be tedious and error prone entering all the quote marks if you're accessing
many pin names. SKiDL lets you enter a single, comma or space-delimited string of
pin names:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10[&#39;GP0 GP1 GP2&#39;]
[Pin U1/1/GP0/BIDIRECTIONAL, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/4/GP2/BIDIRECTIONAL]
</code></pre></div>

<p>Some parts have sequentially-numbered sets of pins like the address and data buses of a RAM.
SKiDL lets you access these pins using a slice-like notation in a string like so:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; ram = Part(&#39;Memory_RAM&#39;, &#39;AS6C1616&#39;)
&gt;&gt;&gt; ram[&#39;DQ[0:2]&#39;]
[Pin U2/29/DQ0/BIDIRECTIONAL, Pin U2/31/DQ1/BIDIRECTIONAL, Pin U2/33/DQ2/BIDIRECTIONAL]
</code></pre></div>

<p>Or you may access the pins in the reverse order:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; ram = Part(&#39;memory&#39;, &#39;sram_512ko&#39;)
&gt;&gt;&gt; ram[&#39;DQ[2:0]&#39;]
[Pin U2/33/DQ2/BIDIRECTIONAL, Pin U2/31/DQ1/BIDIRECTIONAL, Pin U2/29/DQ0/BIDIRECTIONAL]
</code></pre></div>

<p>Some parts (like microcontrollers) have long pin names that list every function a pin
supports (e.g. <code>GP1/AN1/ICSPCLK</code>).
Employing the complete pin name is tedious to enter correctly and
obfuscates which particular function is being used.
SKiDL offers two ways to deal with this: 1) split the pin names into a set of shorter aliases, or
2) match pin names using regular expressions.</p>
<p>If a part has pin names where the subnames are separated by delimiters such as <code>/</code>,
then the subnames for each pin can be assigned as aliases:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10[3].name = &#39;GP1/AN1/ICSPCLK&#39;  # Give pin 3 a long name.
&gt;&gt;&gt; pic10[3].split_name(&#39;/&#39;)           # Split pin 3 name into aliases.
&gt;&gt;&gt; pic10.split_pin_names(&#39;/&#39;)         # Split all pin names into aliases.
&gt;&gt;&gt; pic10[3].aliases                   # Show aliases for pin 3.
{&#39;AN1&#39;, &#39;GP1&#39;, &#39;ICSPCLK&#39;}
&gt;&gt;&gt; pic10[&#39;AN1&#39;] += Net(&#39;analog1&#39;)     # Connect a net using the pin alias.
&gt;&gt;&gt; pic10.AN1 += Net(&#39;analog2&#39;)        # Or access the alias thru an attribute.
</code></pre></div>

<p>You can also split the pin names when you create the part by supplying a string
of delimiter characters:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;, pin_splitters=&#39;/&#39;)
</code></pre></div>

<p>The other way to access a pin with a long name is to use a regular expression.
You'll have to enable regular expression matching for a particular part (it's off by default),
and you'll have to use an odd-looking expression, but here's how it's done:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">pic10</span><span class="p">[</span><span class="mh">3</span><span class="p">].</span><span class="n">name</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="p">&#39;</span><span class="n">GP1</span><span class="o">/</span><span class="n">AN1</span><span class="o">/</span><span class="n">ICSPCLK</span><span class="p">&#39;</span>
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">pic10</span><span class="p">.</span><span class="n">match_pin_regex</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">True</span><span class="w">          </span><span class="p">#</span><span class="w"> </span><span class="n">Enable</span><span class="w"> </span><span class="n">regular</span><span class="w"> </span><span class="n">expression</span><span class="w"> </span><span class="n">matching</span><span class="p">.</span>
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">pic10</span><span class="p">[&#39;.</span><span class="o">*/</span><span class="n">AN1</span><span class="o">/</span><span class="p">.</span><span class="o">*</span><span class="p">&#39;]</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="n">Net</span><span class="p">(&#39;</span><span class="n">analog1</span><span class="p">&#39;)</span><span class="w">   </span><span class="p">#</span><span class="w"> </span><span class="n">I</span><span class="w"> </span><span class="n">told</span><span class="w"> </span><span class="n">you</span><span class="w"> </span><span class="n">the</span><span class="w"> </span><span class="n">expression</span><span class="w"> </span><span class="n">was</span><span class="w"> </span><span class="n">strange</span><span class="o">!</span>
</code></pre></div>

<p>You can avoid explicitly enabling regular expression matching by just creating the expression as
an <code>Rgx</code> like this:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">pic10</span><span class="p">[</span><span class="mh">3</span><span class="p">].</span><span class="n">name</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="p">&#39;</span><span class="n">GP1</span><span class="o">/</span><span class="n">AN1</span><span class="o">/</span><span class="n">ICSPCLK</span><span class="p">&#39;</span>
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">pic10</span><span class="p">[</span><span class="n">Rgx</span><span class="p">(&#39;.</span><span class="o">*/</span><span class="n">AN1</span><span class="o">/</span><span class="p">.</span><span class="o">*</span><span class="p">&#39;)]</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="n">Net</span><span class="p">(&#39;</span><span class="n">analog1</span><span class="p">&#39;)</span><span class="w">  </span><span class="p">#</span><span class="w"> </span><span class="n">No</span><span class="w"> </span><span class="n">need</span><span class="w"> </span><span class="n">to</span><span class="w"> </span><span class="n">manually</span><span class="w"> </span><span class="n">enable</span><span class="w"> </span><span class="n">regular</span><span class="w"> </span><span class="n">expression</span><span class="w"> </span><span class="n">matching</span><span class="o">!</span>
</code></pre></div>

<p>Since you may access pins by number or by name using strings or regular expressions, it's worth
discussing how SKiDL decides which one to select.
When given a pin index, SKiDL stops searching and returns the matching pins as soon as
one of the following conditions succeeds:</p>
<ol>
<li>One or more pin numbers match the index.</li>
<li>One or more pin aliases match the index using standard string matching.</li>
<li>One or more pin names match the index using standard string matching.</li>
<li>One or more pin aliases match the index using regular expression matching.</li>
<li>One or more pin names match the index using regular expression matching.</li>
</ol>
<p>Since SKiDL prioritizes pin number matches over name matches,
what happens when you use a name that is the same as the number of another pin?
For example, a memory chip in a BGA would have pin numbers <code>A1</code>, <code>A2</code>, <code>A3</code>, ... but might
also have address pins named <code>A1</code>, <code>A2</code>, <code>A3</code>, ... .
In order to specifically target either pin numbers or names,
SKiDL provides the <code>p</code> and <code>n</code> part attributes:</p>
<div class="highlight"><pre><span></span><code><span class="n">ram</span><span class="p">[</span><span class="s1">&#39;A1, A2, A3&#39;</span><span class="p">]</span>    <span class="c1"># Selects pin numbers A1, A2 and A3 if the part is a BGA.</span>
<span class="n">ram</span><span class="o">.</span><span class="n">p</span><span class="p">[</span><span class="s1">&#39;A1, A2, A3&#39;</span><span class="p">]</span>  <span class="c1"># Use the p attribute to specifically select pin numbers A1, A2 and A3.</span>
<span class="n">ram</span><span class="o">.</span><span class="n">n</span><span class="p">[</span><span class="s1">&#39;A1, A2, A3&#39;</span><span class="p">]</span>  <span class="c1"># Use the n attribute to specifically select pin names A1, A2 and A3.</span>
</code></pre></div>

<p><code>Part</code> objects also provide the <code>get_pins()</code> function which can select pins in even more ways.
For example, this would get every bidirectional pin of the processor:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10.get_pins(func=Pin.BIDIR)
[Pin U1/1/GP0/BIDIRECTIONAL, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/4/GP2/BIDIRECTIONAL]
</code></pre></div>

<p>You can access part pins algorithmically in a loop like this:</p>
<div class="highlight"><pre><span></span><code><span class="k">for</span> <span class="n">p</span> <span class="ow">in</span> <span class="n">pic10</span><span class="o">.</span><span class="n">get_pins</span><span class="p">():</span>
  <span class="o">&lt;</span><span class="n">do</span> <span class="n">something</span> <span class="k">with</span> <span class="n">p</span><span class="o">&gt;</span>
</code></pre></div>

<p>Or do the same thing using a <code>Part</code> object as an iterator:</p>
<div class="highlight"><pre><span></span><code><span class="k">for</span> <span class="n">p</span> <span class="ow">in</span> <span class="n">pic10</span><span class="p">:</span>
  <span class="o">&lt;</span><span class="n">do</span> <span class="n">something</span> <span class="k">with</span> <span class="n">p</span><span class="o">&gt;</span>
</code></pre></div>

<p>It's possible that <code>get_pins</code> will not generate the part's pins in order of increasing pin number.
If that's needed, then use the <code>ordered_pins</code> property to get the
pin numbers of all the part's pins in ascending order:</p>
<div class="highlight"><pre><span></span><code><span class="k">for</span> <span class="n">num</span> <span class="ow">in</span> <span class="n">pic10</span><span class="o">.</span><span class="n">ordered_pins</span><span class="p">:</span>
  <span class="o">&lt;</span> <span class="n">do</span> <span class="n">something</span> <span class="k">with</span> <span class="n">pic10</span><span class="p">[</span><span class="n">num</span><span class="p">]</span><span class="o">&gt;</span>
</code></pre></div>

<h3 id="accessing-bus-lines">Accessing Bus Lines</h3>
<p>Accessing the individual lines of a bus works similarly to accessing part pins:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; a = Net(&#39;NET_A&#39;)  # Create a named net.
&gt;&gt;&gt; b = Bus(&#39;BUS_B&#39;, 4, a)  # Create a five-bit bus.
&gt;&gt;&gt; b
BUS_B:
        BUS_B0:  # Note how the individual lines of the bus are named.
        BUS_B1:
        BUS_B2:
        BUS_B3:
        NET_A:   # The last net retains its original name.

&gt;&gt;&gt; b[0]  # Get the first line of the bus.
BUS_B0:

&gt;&gt;&gt; b[2,4]  # Get the second and fourth bus lines.
[BUS_B2: , NET_A: ]

&gt;&gt;&gt; b[3:0]  # Get the first four bus lines in reverse order.
[BUS_B3: , BUS_B2: , BUS_B1: , BUS_B0: ]

&gt;&gt;&gt; b[-1]  # Get the last bus line.
NET_A: 

&gt;&gt;&gt; b[&#39;BUS_B.*&#39;]  # Get all the bus lines except the last one.
[BUS_B0: , BUS_B1: , BUS_B2: , BUS_B3: ]

&gt;&gt;&gt; b[&#39;NET_A&#39;]  # Get the last bus line.
NET_A:

&gt;&gt;&gt; for line in b:  # Access lines in bus using bus as an iterator.
...:    print(line)
...:
BUS_B0:
BUS_B1:
BUS_B2:
BUS_B3:
NET_A:
</code></pre></div>

<h2 id="making-connections">Making Connections</h2>
<p>Pins, nets, parts and buses can all be connected together in various ways, but
the <strong>primary rule</strong> of SKiDL connections is:</p>
<blockquote>
<p><strong>The <code>+=</code> operator is the only way to make connections!</strong></p>
</blockquote>
<p>At times you'll mistakenly try to make connections using the 
assignment operator (<code>=</code>). In many cases, SKiDL warns you if you do that,
but there are situations where it can't (because
Python is a general-purpose programming language where
assignment is a necessary operation).
So remember the primary rule!</p>
<p>After the primary rule, the next thing to remember is that SKiDL's main
purpose is creating netlists. To that end, it handles four basic, connection operations:</p>
<p><strong>Net-to-Net</strong>:
    Connecting one net to another <em>merges</em> the pins on both nets
    into a single, larger net.</p>
<p><strong>Pin-to-Net</strong>:
    A pin is connected to a net, adding it to the list of pins
    connected to that net. If the pin is already attached to other nets,
    then those nets are merged with this net.</p>
<p><strong>Net-to-Pin</strong>: 
    This is the same as doing a pin-to-net connection.</p>
<p><strong>Pin-to-Pin</strong>:
    A net is created and both pins are attached to it. If one or
    both pins are already connected to other nets, then those nets are merged
    with the newly-created.</p>
<p>For each type of connection operation, there are three variants based on
the number of things being connected:</p>
<p><strong>One-to-One</strong>:
    This is the most frequent type of connection, for example, connecting one
    pin to another or connecting a pin to a net.</p>
<p><strong>One-to-Many</strong>:
    This mainly occurs when multiple pins are connected to the same net, like
    when multiple ground pins of a chip are connected to the circuit ground net.</p>
<p><strong>Many-to-Many</strong>:
    This usually involves bus connections to a part, such as connecting
    a bus to the data or address pins of a processor. For this variant, there must be the
    same number of things to connect in each set, e.g. you can't connect
    three pins to four nets.</p>
<p>As a first example, let's connect a net to a pin on a part:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;)  # Get a part.
&gt;&gt;&gt; io = Net(&#39;IO_NET&#39;)  # Create a net.
&gt;&gt;&gt; pic10.GP0 += io    # Connect the net to a part pin.
&gt;&gt;&gt; io                  # Show the pins connected to the net.
IO_NET: Pin U5/1/GP0/BIDIRECTIONAL
</code></pre></div>

<p>You may do the same operation in reverse by connecting the part pin to the net
with the same result:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;)
&gt;&gt;&gt; io = Net(&#39;IO_NET&#39;)
&gt;&gt;&gt; io += pic10.GP0     # Connect a part pin to the net.
&gt;&gt;&gt; io
IO_NET_1: Pin U6/1/GP0/BIDIRECTIONAL
</code></pre></div>

<p>You may also connect a pin directly to another pin.
In this case, an <em>implicit net</em> will be created between the pins that you can
access using the <code>net</code> attribute of either part pin:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">pic10</span>.<span class="nv">GP1</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="nv">pic10</span>.<span class="nv">GP2</span><span class="w">  </span>#<span class="w"> </span><span class="k">Connect</span><span class="w"> </span><span class="nv">two</span><span class="w"> </span><span class="nv">pins</span><span class="w"> </span><span class="nv">together</span>.
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">pic10</span>.<span class="nv">GP1</span>.<span class="nv">net</span><span class="w">           </span>#<span class="w"> </span><span class="k">Show</span><span class="w"> </span><span class="nv">the</span><span class="w"> </span><span class="nv">net</span><span class="w"> </span><span class="nv">connected</span><span class="w"> </span><span class="nv">to</span><span class="w"> </span><span class="nv">the</span><span class="w"> </span><span class="nv">pin</span>.
<span class="nv">N</span><span class="mh">$1</span>:<span class="w"> </span><span class="nv">Pin</span><span class="w"> </span><span class="nv">U6</span><span class="o">/</span><span class="mi">3</span><span class="o">/</span><span class="nv">GP1</span><span class="o">/</span><span class="nv">BIDIRECTIONAL</span>,<span class="w"> </span><span class="nv">Pin</span><span class="w"> </span><span class="nv">U6</span><span class="o">/</span><span class="mi">4</span><span class="o">/</span><span class="nv">GP2</span><span class="o">/</span><span class="nv">BIDIRECTIONAL</span>
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">pic10</span>.<span class="nv">GP2</span>.<span class="nv">net</span><span class="w">           </span>#<span class="w"> </span><span class="k">Show</span><span class="w"> </span><span class="nv">the</span><span class="w"> </span><span class="nv">net</span><span class="w"> </span><span class="nv">connected</span><span class="w"> </span><span class="nv">to</span><span class="w"> </span><span class="nv">the</span><span class="w"> </span><span class="nv">other</span><span class="w"> </span><span class="nv">pin</span>.<span class="w"> </span><span class="nv">Same</span><span class="w"> </span><span class="nv">thing</span><span class="o">!</span>
<span class="nv">N</span><span class="mh">$1</span>:<span class="w"> </span><span class="nv">Pin</span><span class="w"> </span><span class="nv">U6</span><span class="o">/</span><span class="mi">3</span><span class="o">/</span><span class="nv">GP1</span><span class="o">/</span><span class="nv">BIDIRECTIONAL</span>,<span class="w"> </span><span class="nv">Pin</span><span class="w"> </span><span class="nv">U6</span><span class="o">/</span><span class="mi">4</span><span class="o">/</span><span class="nv">GP2</span><span class="o">/</span><span class="nv">BIDIRECTIONAL</span>
</code></pre></div>

<p>You can connect multiple pins, all at once:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;) 
&gt;&gt;&gt; pic10[1] += pic10[2,3,6]
&gt;&gt;&gt; pic10[1].net
N$1: Pin U7/1/GP0/BIDIRECTIONAL, Pin U7/2/VSS/POWER-IN, Pin U7/3/GP1/BIDIRECTIONAL, Pin U7/6/GP3/INPUT
</code></pre></div>

<p>Or you may do it incrementally:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;) 
&gt;&gt;&gt; pic10[1] += pic10[2]
&gt;&gt;&gt; pic10[1] += pic10[3]
&gt;&gt;&gt; pic10[1] += pic10[6]
&gt;&gt;&gt; pic10[1].net
N$1: Pin U8/1/GP0/BIDIRECTIONAL, Pin U8/2/VSS/POWER-IN, Pin U8/3/GP1/BIDIRECTIONAL, Pin U8/6/GP3/INPUT
</code></pre></div>

<p>If you connect pins on separate nets together, then all the pins are merged onto the same net:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;) 
&gt;&gt;&gt; pic10[1] += pic10[2]  # Put pins 1 &amp; 2 on one net.
&gt;&gt;&gt; pic10[3] += pic10[4]  # Put pins 3 &amp; 4 on another net.
&gt;&gt;&gt; pic10[1] += pic10[4]  # Connect two pins from different nets.
&gt;&gt;&gt; pic10[3].net          # Now all the pins are on the same net!
N$9: Pin U9/1/GP0/BIDIRECTIONAL, Pin U9/2/VSS/POWER-IN, Pin U9/3/GP1/BIDIRECTIONAL, Pin U9/4/GP2/BIDIRECTIONAL
</code></pre></div>

<p>Here's an example of connecting a three-bit bus to three pins on a part:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;) 
&gt;&gt;&gt; b = Bus(&#39;GP&#39;, 3)                # Create a 3-bit bus.
&gt;&gt;&gt; pic10[&#39;GP2 GP1 GP0&#39;] += b[2:0]  # Connect bus to part pins, one-to-one.
&gt;&gt;&gt; b
GP:
        GP0: Pin U10/1/GP0/BIDIRECTIONAL
        GP1: Pin U10/3/GP1/BIDIRECTIONAL
        GP2: Pin U10/4/GP2/BIDIRECTIONAL
</code></pre></div>

<p>But SKiDL will warn you if there aren't the same number of things to
connect on each side:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">pic10</span><span class="p">[</span><span class="mi">4</span><span class="p">,</span><span class="mi">3</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="n">b</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">0</span><span class="p">]</span><span class="w">  </span><span class="c1"># Too few bus lines for the pins!</span>
<span class="n">ERROR</span><span class="p">:</span><span class="w"> </span><span class="n">Connection</span><span class="w"> </span><span class="n">mismatch</span><span class="w"> </span><span class="mi">3</span><span class="w"> </span><span class="o">!=</span><span class="w"> </span><span class="mi">2</span><span class="o">!</span>
<span class="o">---------------------------------------------------------------------------</span>
<span class="n">ValueError</span><span class="w">                                </span><span class="n">Traceback</span><span class="w"> </span><span class="p">(</span><span class="n">most</span><span class="w"> </span><span class="n">recent</span><span class="w"> </span><span class="n">call</span><span class="w"> </span><span class="n">last</span><span class="p">)</span>
<span class="o">&lt;</span><span class="n">ipython</span><span class="o">-</span><span class="n">input</span><span class="o">-</span><span class="mi">83</span><span class="o">-</span><span class="mi">48</span><span class="n">a1e46383fe</span><span class="o">&gt;</span><span class="w"> </span><span class="ow">in</span><span class="w"> </span><span class="o">&lt;</span><span class="n">module</span><span class="o">&gt;</span>
<span class="o">----&gt;</span><span class="w"> </span><span class="mi">1</span><span class="w"> </span><span class="n">pic10</span><span class="p">[</span><span class="mi">4</span><span class="p">,</span><span class="mi">3</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="n">b</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">0</span><span class="p">]</span>

<span class="o">/</span><span class="n">media</span><span class="o">/</span><span class="n">devb</span><span class="o">/</span><span class="n">Main</span><span class="o">/</span><span class="n">devbisme</span><span class="o">/</span><span class="n">KiCad</span><span class="o">/</span><span class="n">tools</span><span class="o">/</span><span class="n">skidl</span><span class="o">/</span><span class="n">skidl</span><span class="o">/</span><span class="n">netpinlist</span><span class="o">.</span><span class="n">py</span><span class="w"> </span><span class="ow">in</span><span class="w"> </span><span class="n">__iadd__</span><span class="p">(</span><span class="bp">self</span><span class="p">,</span><span class="w"> </span><span class="o">*</span><span class="n">nets_pins_buses</span><span class="p">)</span>
<span class="w">     </span><span class="mi">60</span><span class="w">         </span><span class="k">if</span><span class="w"> </span><span class="n">len</span><span class="p">(</span><span class="n">nets_pins</span><span class="p">)</span><span class="w"> </span><span class="o">!=</span><span class="w"> </span><span class="n">len</span><span class="p">(</span><span class="bp">self</span><span class="p">):</span>
<span class="w">     </span><span class="mi">61</span><span class="w">             </span><span class="k">if</span><span class="w"> </span><span class="n">Net</span><span class="w"> </span><span class="ow">in</span><span class="w"> </span><span class="p">[</span><span class="n">type</span><span class="p">(</span><span class="n">item</span><span class="p">)</span><span class="w"> </span><span class="k">for</span><span class="w"> </span><span class="n">item</span><span class="w"> </span><span class="ow">in</span><span class="w"> </span><span class="bp">self</span><span class="p">]</span><span class="w"> </span><span class="ow">or</span><span class="w"> </span><span class="n">len</span><span class="p">(</span><span class="n">nets_pins</span><span class="p">)</span><span class="w"> </span><span class="o">&gt;</span><span class="w"> </span><span class="mi">1</span><span class="p">:</span>
<span class="o">---&gt;</span><span class="w"> </span><span class="mi">62</span><span class="w">                 </span><span class="n">log_and_raise</span><span class="p">(</span>
<span class="w">     </span><span class="mi">63</span><span class="w">                     </span><span class="n">logger</span><span class="p">,</span>
<span class="w">     </span><span class="mi">64</span><span class="w">                     </span><span class="n">ValueError</span><span class="p">,</span>

<span class="o">/</span><span class="n">media</span><span class="o">/</span><span class="n">devb</span><span class="o">/</span><span class="n">Main</span><span class="o">/</span><span class="n">devbisme</span><span class="o">/</span><span class="n">KiCad</span><span class="o">/</span><span class="n">tools</span><span class="o">/</span><span class="n">skidl</span><span class="o">/</span><span class="n">skidl</span><span class="o">/</span><span class="n">utilities</span><span class="o">.</span><span class="n">py</span><span class="w"> </span><span class="ow">in</span><span class="w"> </span><span class="n">log_and_raise</span><span class="p">(</span><span class="n">logger_in</span><span class="p">,</span><span class="w"> </span><span class="n">exc_class</span><span class="p">,</span><span class="w"> </span><span class="n">message</span><span class="p">)</span>
<span class="w">    </span><span class="mi">785</span><span class="w"> </span><span class="n">def</span><span class="w"> </span><span class="n">log_and_raise</span><span class="p">(</span><span class="n">logger_in</span><span class="p">,</span><span class="w"> </span><span class="n">exc_class</span><span class="p">,</span><span class="w"> </span><span class="n">message</span><span class="p">):</span>
<span class="w">    </span><span class="mi">786</span><span class="w">     </span><span class="n">logger_in</span><span class="o">.</span><span class="n">error</span><span class="p">(</span><span class="n">message</span><span class="p">)</span>
<span class="o">--&gt;</span><span class="w"> </span><span class="mi">787</span><span class="w">     </span><span class="n">raise</span><span class="w"> </span><span class="n">exc_class</span><span class="p">(</span><span class="n">message</span><span class="p">)</span>
<span class="w">    </span><span class="mi">788</span><span class="w"> </span>
<span class="w">    </span><span class="mi">789</span><span class="w"> </span>

<span class="n">ValueError</span><span class="p">:</span><span class="w"> </span><span class="n">Connection</span><span class="w"> </span><span class="n">mismatch</span><span class="w"> </span><span class="mi">3</span><span class="w"> </span><span class="o">!=</span><span class="w"> </span><span class="mi">2</span><span class="o">!</span>
</code></pre></div>

<h2 id="making-serial-parallel-and-tee-networks">Making Serial, Parallel, and Tee Networks</h2>
<p>The previous section showed some general-purpose techniques for connecting parts,
but SKiDL also has some
<a href="https://devbisme.github.io/skidl/docs/_site/blog/sweetening-skidl">specialized syntax</a>
for wiring two-pin components in parallel or serial.
For example, here is a network of four resistors connected in series
between power and ground:</p>
<div class="highlight"><pre><span></span><code><span class="n">vcc</span><span class="p">,</span> <span class="n">gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;VCC&#39;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;GND&#39;</span><span class="p">)</span>
<span class="n">r1</span><span class="p">,</span> <span class="n">r2</span><span class="p">,</span> <span class="n">r3</span><span class="p">,</span> <span class="n">r4</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;R&#39;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)</span> <span class="o">*</span> <span class="mi">4</span>
<span class="n">ser_ntwk</span> <span class="o">=</span> <span class="n">vcc</span> <span class="o">&amp;</span> <span class="n">r1</span> <span class="o">&amp;</span> <span class="n">r2</span> <span class="o">&amp;</span> <span class="n">r3</span> <span class="o">&amp;</span> <span class="n">r4</span> <span class="o">&amp;</span> <span class="n">gnd</span>
</code></pre></div>

<p>It's also possible to connect the resistors in parallel between power and ground:</p>
<div class="highlight"><pre><span></span><code><span class="n">par_ntwk</span> <span class="o">=</span> <span class="n">vcc</span> <span class="o">&amp;</span> <span class="p">(</span><span class="n">r1</span> <span class="o">|</span> <span class="n">r2</span> <span class="o">|</span> <span class="n">r3</span> <span class="o">|</span> <span class="n">r4</span><span class="p">)</span> <span class="o">&amp;</span> <span class="n">gnd</span>
</code></pre></div>

<p>Or you can do something like placing pairs of resistors in series and then paralleling
those combinations like this:</p>
<div class="highlight"><pre><span></span><code><span class="n">combo_ntwk</span> <span class="o">=</span> <span class="n">vcc</span> <span class="o">&amp;</span> <span class="p">((</span><span class="n">r1</span> <span class="o">&amp;</span> <span class="n">r2</span><span class="p">)</span> <span class="o">|</span> <span class="p">(</span><span class="n">r3</span> <span class="o">&amp;</span> <span class="n">r4</span><span class="p">))</span> <span class="o">&amp;</span> <span class="n">gnd</span>
</code></pre></div>

<p>The examples above work with <em>non-polarized</em> components, but what about parts
like diodes? In that case, you have to specify the pins <em>explicitly</em> with the
first pin connected to the preceding part and the second pin to the following part:</p>
<div class="highlight"><pre><span></span><code><span class="n">d1</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;D&#39;</span><span class="p">)</span>
<span class="n">polar_ntwk</span> <span class="o">=</span> <span class="n">vcc</span> <span class="o">&amp;</span> <span class="n">r1</span> <span class="o">&amp;</span> <span class="n">d1</span><span class="p">[</span><span class="s1">&#39;A,K&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">gnd</span>  <span class="c1"># Diode anode connected to resistor and cathode to ground.</span>
</code></pre></div>

<p>Explicitly listing the pins also lets you use multi-pin parts with networks.
For example, here's an NPN-transistor amplifier:</p>
<div class="highlight"><pre><span></span><code><span class="n">q1</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;Q_NPN_ECB&#39;</span><span class="p">)</span>
<span class="n">ntwk_ce</span> <span class="o">=</span> <span class="n">vcc</span> <span class="o">&amp;</span> <span class="n">r1</span> <span class="o">&amp;</span> <span class="n">q1</span><span class="p">[</span><span class="s1">&#39;C,E&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">gnd</span>  <span class="c1"># VCC through load resistor to collector and emitter attached to ground.</span>
<span class="n">ntwk_b</span> <span class="o">=</span> <span class="n">r2</span> <span class="o">&amp;</span> <span class="n">q1</span><span class="p">[</span><span class="s1">&#39;B&#39;</span><span class="p">]</span>  <span class="c1"># Resistor attached to base.</span>
</code></pre></div>

<p>That's all well and good, but how do you connect to internal points in these networks where
the interesting things are happening?
For instance, how do you apply an input to the transistor circuit and then connect
to the output?
One way is by inserting nets <em>inside</em> the network:</p>
<div class="highlight"><pre><span></span><code><span class="n">inp</span><span class="p">,</span> <span class="n">outp</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;INPUT&#39;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;OUTPUT&#39;</span><span class="p">)</span>
<span class="n">ntwk_ce</span> <span class="o">=</span> <span class="n">vcc</span> <span class="o">&amp;</span> <span class="n">r1</span> <span class="o">&amp;</span> <span class="n">outp</span> <span class="o">&amp;</span> <span class="n">q1</span><span class="p">[</span><span class="s1">&#39;C,E&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">gnd</span>  <span class="c1"># Connect net outp to the junction of the resistor and transistor collector.</span>
<span class="n">ntwk_b</span> <span class="o">=</span> <span class="n">inp</span> <span class="o">&amp;</span> <span class="n">r2</span> <span class="o">&amp;</span> <span class="n">q1</span><span class="p">[</span><span class="s1">&#39;B&#39;</span><span class="p">]</span>  <span class="c1"># Connect net inp to the resistor driving the transistor base.</span>
</code></pre></div>

<p>After that, the <code>inp</code> and <code>outp</code> nets can be connected to other points in the circuit.</p>
<p>Not all networks are composed of parts in series or parallel, for example the
<a href="https://www.eeweb.com/tools/pi-match"><em>Pi matching network</em></a>.
This can be described using the <code>tee()</code> function like so:</p>
<div class="highlight"><pre><span></span><code><span class="n">inp</span><span class="p">,</span> <span class="n">outp</span><span class="p">,</span> <span class="n">gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;INPUT&#39;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;OUTPUT&#39;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;GND&#39;</span><span class="p">)</span>
<span class="n">l</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;L&#39;</span><span class="p">)</span>
<span class="n">cs</span><span class="p">,</span> <span class="n">cl</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;C&#39;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)</span> <span class="o">*</span> <span class="mi">2</span>
<span class="n">pi_ntwk</span> <span class="o">=</span> <span class="n">inp</span> <span class="o">&amp;</span> <span class="n">tee</span><span class="p">(</span><span class="n">cs</span> <span class="o">&amp;</span> <span class="n">gnd</span><span class="p">)</span> <span class="o">&amp;</span> <span class="n">l</span> <span class="o">&amp;</span> <span class="n">tee</span><span class="p">(</span><span class="n">cl</span> <span class="o">&amp;</span> <span class="n">gnd</span><span class="p">)</span> <span class="o">&amp;</span> <span class="n">outp</span>
</code></pre></div>

<p>The <code>tee</code> function takes any network as its argument and returns the first node of
that network to be connected into the higher-level network.
The network passed to <code>tee</code> can be arbitrarily complex, including any
combination of parts, <code>&amp;</code>'s, <code>|</code>'s, and <code>tee</code>'s.</p>
<h2 id="aliases">Aliases</h2>
<p>Aliases let you assign a more descriptive name to a part, pin, net, or bus without
affecting the original name.
This is most useful in assigning names to pins to describe their functions.</p>
<div class="highlight"><pre><span></span><code><span class="n">r</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;R&#39;</span><span class="p">)</span>
<span class="n">r</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span> <span class="o">+=</span> <span class="n">vcc</span>  <span class="c1"># Connect one end of resistor to VCC net.</span>
<span class="n">r</span><span class="p">[</span><span class="mi">2</span><span class="p">]</span><span class="o">.</span><span class="n">aliases</span> <span class="o">+=</span> <span class="s1">&#39;pullup&#39;</span>  <span class="c1"># Add the alias &#39;pullup&#39; to the other end of the resistor.</span>

<span class="n">uc</span><span class="p">[</span><span class="s1">&#39;RESET&#39;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">r</span><span class="p">[</span><span class="s1">&#39;pullup&#39;</span><span class="p">]</span>  <span class="c1"># Connect the pullup pin to the reset pin of a microcontroller.</span>
</code></pre></div>

<p>To see the assigned aliases, just use the <code>aliases</code> attribute:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; r = Part(&#39;Device&#39;, &#39;R&#39;)
&gt;&gt;&gt; r[2].aliases += &#39;pullup&#39;
&gt;&gt;&gt; r[2].aliases += &#39;aklgjh&#39;  # Some nonsense alias.
&gt;&gt;&gt; r[2].aliases

{&#39;aklghj&#39;, &#39;pullup&#39;}
</code></pre></div>

<h2 id="units-within-parts">Units Within Parts</h2>
<p>Some components are comprised of smaller operational <em>units</em>.
For example, an operational amplifier chip might contain two individual opamp units,
each capable of operating on their own set of inputs and outputs.</p>
<p>Library parts may already have predefined units, but you can add them to any part.
For example, a four-pin <em>resistor network</em> might contain two resistors:
one attached between pins 1 and 4, and the other bewtween pins 2 and 3.
Each resistor could be assigned to a unit as follows:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">rn</span><span class="w"> </span><span class="p">=</span><span class="w"> </span><span class="nx">Part</span><span class="p">(</span><span class="s">&quot;Device&quot;</span><span class="p">,</span><span class="w"> </span><span class="err">&#39;</span><span class="nx">R_Pack02</span><span class="err">&#39;</span><span class="p">)</span>
<span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">rn</span><span class="p">.</span><span class="nx">make_unit</span><span class="p">(</span><span class="sc">&#39;A&#39;</span><span class="p">,</span><span class="w"> </span><span class="mi">1</span><span class="p">,</span><span class="w"> </span><span class="mi">4</span><span class="p">)</span><span class="w">  </span><span class="err">#</span><span class="w"> </span><span class="nx">Make</span><span class="w"> </span><span class="nx">a</span><span class="w"> </span><span class="nx">unit</span><span class="w"> </span><span class="nx">called</span><span class="w"> </span><span class="sc">&#39;A&#39;</span><span class="w"> </span><span class="k">for</span><span class="w"> </span><span class="nx">the</span><span class="w"> </span><span class="nx">first</span><span class="w"> </span><span class="nx">resistor</span><span class="p">.</span>

<span class="w"> </span><span class="nx">R_Pack02</span><span class="w"> </span><span class="p">():</span><span class="w"> </span><span class="mi">2</span><span class="w"> </span><span class="nx">Resistor</span><span class="w"> </span><span class="nx">network</span><span class="p">,</span><span class="w"> </span><span class="nx">parallel</span><span class="w"> </span><span class="nx">topology</span><span class="p">,</span><span class="w"> </span><span class="nx">DIP</span><span class="w"> </span><span class="kn">package</span>
<span class="w">    </span><span class="nx">Pin</span><span class="w"> </span><span class="nx">RN1</span><span class="o">/</span><span class="mi">4</span><span class="o">/</span><span class="nx">R1</span><span class="m m-Double">.2</span><span class="o">/</span><span class="nx">PASSIVE</span>
<span class="w">    </span><span class="nx">Pin</span><span class="w"> </span><span class="nx">RN1</span><span class="o">/</span><span class="mi">1</span><span class="o">/</span><span class="nx">R1</span><span class="m m-Double">.1</span><span class="o">/</span><span class="nx">PASSIVE</span>

<span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">rn</span><span class="p">.</span><span class="nx">make_unit</span><span class="p">(</span><span class="sc">&#39;B&#39;</span><span class="p">,</span><span class="w"> </span><span class="mi">2</span><span class="p">,</span><span class="w"> </span><span class="mi">3</span><span class="p">)</span><span class="w">  </span><span class="err">#</span><span class="w"> </span><span class="nx">Now</span><span class="w"> </span><span class="nx">make</span><span class="w"> </span><span class="nx">a</span><span class="w"> </span><span class="nx">unit</span><span class="w"> </span><span class="nx">called</span><span class="w"> </span><span class="sc">&#39;B&#39;</span><span class="w"> </span><span class="k">for</span><span class="w"> </span><span class="nx">the</span><span class="w"> </span><span class="nx">second</span><span class="w"> </span><span class="nx">resistor</span><span class="p">.</span>

<span class="w"> </span><span class="nx">R_Pack02</span><span class="w"> </span><span class="p">():</span><span class="w"> </span><span class="mi">2</span><span class="w"> </span><span class="nx">Resistor</span><span class="w"> </span><span class="nx">network</span><span class="p">,</span><span class="w"> </span><span class="nx">parallel</span><span class="w"> </span><span class="nx">topology</span><span class="p">,</span><span class="w"> </span><span class="nx">DIP</span><span class="w"> </span><span class="kn">package</span>
<span class="w">    </span><span class="nx">Pin</span><span class="w"> </span><span class="nx">RN1</span><span class="o">/</span><span class="mi">2</span><span class="o">/</span><span class="nx">R2</span><span class="m m-Double">.1</span><span class="o">/</span><span class="nx">PASSIVE</span>
<span class="w">    </span><span class="nx">Pin</span><span class="w"> </span><span class="nx">RN1</span><span class="o">/</span><span class="mi">3</span><span class="o">/</span><span class="nx">R2</span><span class="m m-Double">.2</span><span class="o">/</span><span class="nx">PASSIVE</span>
</code></pre></div>

<p>Once the units are defined, you may use them just like any part:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">rn</span>.<span class="nv">unit</span>[<span class="s1">&#39;A&#39;</span>][<span class="mi">1</span>,<span class="mi">4</span>]<span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="nv">Net</span><span class="ss">()</span>,<span class="w"> </span><span class="nv">Net</span><span class="ss">()</span><span class="w">  </span>#<span class="w"> </span><span class="k">Connect</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">A</span><span class="w"> </span><span class="nv">to</span><span class="w"> </span><span class="nv">two</span><span class="w"> </span><span class="nv">nets</span>.
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">rn</span>.<span class="nv">unit</span>[<span class="s1">&#39;B&#39;</span>][<span class="mi">2</span>,<span class="mi">3</span>]<span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="nv">rn</span>.<span class="nv">unit</span>[<span class="s1">&#39;A&#39;</span>][<span class="mi">1</span>,<span class="mi">4</span>]<span class="w">  </span>#<span class="w"> </span><span class="k">Connect</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">B</span><span class="w"> </span><span class="nv">in</span><span class="w"> </span><span class="nv">parallel</span><span class="w"> </span><span class="nv">with</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">A</span>.
</code></pre></div>

<p>Now this isn't all that useful because you still have to remember which pins
are assigned to each unit, and if you wanted to swap the resistors you would have
to change the unit names <em>and the pins numbers!</em>.
In order to get around this inconvenience, you could assign aliases to each
pin like this:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">rn</span><span class="p">[</span><span class="mi">1</span><span class="p">].</span><span class="nx">aliases</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="sc">&#39;L&#39;</span><span class="w"> </span><span class="err">#</span><span class="w"> </span><span class="nx">Alias</span><span class="w"> </span><span class="sc">&#39;L&#39;</span><span class="w"> </span><span class="nx">of</span><span class="w"> </span><span class="nx">pin</span><span class="w"> </span><span class="mi">1</span><span class="w"> </span><span class="nx">on</span><span class="w"> </span><span class="nx">left</span><span class="o">-</span><span class="nx">side</span><span class="w"> </span><span class="nx">of</span><span class="w"> </span><span class="kn">package</span><span class="p">.</span>
<span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">rn</span><span class="p">[</span><span class="mi">4</span><span class="p">].</span><span class="nx">aliases</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="sc">&#39;R&#39;</span><span class="w"> </span><span class="err">#</span><span class="w"> </span><span class="nx">Alias</span><span class="w"> </span><span class="sc">&#39;R&#39;</span><span class="w"> </span><span class="nx">of</span><span class="w"> </span><span class="nx">pin</span><span class="w"> </span><span class="mi">4</span><span class="w"> </span><span class="nx">on</span><span class="w"> </span><span class="nx">right</span><span class="o">-</span><span class="nx">side</span><span class="w"> </span><span class="nx">of</span><span class="w"> </span><span class="kn">package</span><span class="p">.</span>
<span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">rn</span><span class="p">[</span><span class="mi">2</span><span class="p">].</span><span class="nx">aliases</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="sc">&#39;L&#39;</span><span class="w"> </span><span class="err">#</span><span class="w"> </span><span class="nx">Alias</span><span class="w"> </span><span class="sc">&#39;L&#39;</span><span class="w"> </span><span class="nx">of</span><span class="w"> </span><span class="nx">pin</span><span class="w"> </span><span class="mi">2</span><span class="w"> </span><span class="nx">on</span><span class="w"> </span><span class="nx">left</span><span class="o">-</span><span class="nx">side</span><span class="p">.</span>
<span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">rn</span><span class="p">[</span><span class="mi">3</span><span class="p">].</span><span class="nx">aliases</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="sc">&#39;R&#39;</span><span class="w"> </span><span class="err">#</span><span class="w"> </span><span class="nx">Alias</span><span class="w"> </span><span class="sc">&#39;R&#39;</span><span class="w"> </span><span class="nx">of</span><span class="w"> </span><span class="nx">pin</span><span class="w"> </span><span class="mi">3</span><span class="w"> </span><span class="nx">on</span><span class="w"> </span><span class="nx">right</span><span class="o">-</span><span class="nx">side</span><span class="p">.</span>
</code></pre></div>

<p>Now the same connections can be made using the pin aliases:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">rn</span>.<span class="nv">unit</span>[<span class="s1">&#39;A&#39;</span>][<span class="s1">&#39;L,R&#39;</span>]<span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="nv">Net</span><span class="ss">()</span>,<span class="w"> </span><span class="nv">Net</span><span class="ss">()</span><span class="w">  </span>#<span class="w"> </span><span class="k">Connect</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">A</span><span class="w"> </span><span class="nv">to</span><span class="w"> </span><span class="nv">two</span><span class="w"> </span><span class="nv">nets</span>.
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">rn</span>.<span class="nv">unit</span>[<span class="s1">&#39;B&#39;</span>][<span class="s1">&#39;L,R&#39;</span>]<span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="nv">rn</span>.<span class="nv">unit</span>[<span class="s1">&#39;A&#39;</span>][<span class="s1">&#39;L,R&#39;</span>]<span class="w">  </span>#<span class="w"> </span><span class="k">Connect</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">B</span><span class="w"> </span><span class="nv">in</span><span class="w"> </span><span class="nv">parallel</span><span class="w"> </span><span class="nv">with</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">A</span>.
</code></pre></div>

<p>In this case, if you wanted to swap the A and B resistors, you only need to change
their unit labels.
The pin aliases don't need to be altered.</p>
<p>If you find the <code>unit[...]</code> notation cumbersome, units can also be accessed by
using their names as attributes:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">rn</span>.<span class="nv">A</span>[<span class="s1">&#39;L,R&#39;</span>]<span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="nv">Net</span><span class="ss">()</span>,<span class="w"> </span><span class="nv">Net</span><span class="ss">()</span><span class="w">  </span>#<span class="w"> </span><span class="k">Connect</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">A</span><span class="w"> </span><span class="nv">to</span><span class="w"> </span><span class="nv">two</span><span class="w"> </span><span class="nv">nets</span>.
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">rn</span>.<span class="nv">B</span>[<span class="s1">&#39;L,R&#39;</span>]<span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="nv">rn</span>.<span class="nv">A</span>[<span class="s1">&#39;L,R&#39;</span>]<span class="w">   </span>#<span class="w"> </span><span class="k">Connect</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">B</span><span class="w"> </span><span class="nv">in</span><span class="w"> </span><span class="nv">parallel</span><span class="w"> </span><span class="nv">with</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">A</span>.
</code></pre></div>

<h2 id="part-and-net-classes">Part and Net Classes</h2>
<p>SKiDL supports part and net classes for applying attributes to groups of components and nets.
Classes provide a systematic, consistent way to manage design constraints, manufacturing requirements,
and electrical characteristics across complex hierarchical designs.</p>
<p>Classes can be assigned individually to parts and nets, or hierarchically through the circuit
structure.</p>
<h3 id="individual-part-and-net-classes">Individual Part and Net Classes</h3>
<p>You can assign classes directly to individual parts and nets to specify design attributes like
manufacturing requirements or electrical characteristics. Multiple classes can be assigned
with higher priority classes taking precedence over those with lower priority.</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>

<span class="c1"># Create part classes for different component categories.</span>
<span class="n">passive_parts</span> <span class="o">=</span> <span class="n">PartClass</span><span class="p">(</span><span class="s2">&quot;passive_parts&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">1</span><span class="p">,</span> <span class="n">tolerance</span><span class="o">=</span><span class="s2">&quot;5%&quot;</span><span class="p">)</span>
<span class="n">active_parts</span> <span class="o">=</span> <span class="n">PartClass</span><span class="p">(</span><span class="s2">&quot;active_parts&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">5</span><span class="p">)</span>
<span class="n">power_parts</span> <span class="o">=</span> <span class="n">PartClass</span><span class="p">(</span><span class="s2">&quot;power_parts&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">10</span><span class="p">,</span> <span class="n">tolerance</span><span class="o">=</span><span class="s2">&quot;1%&quot;</span><span class="p">,</span> <span class="n">temp_rating</span><span class="o">=</span><span class="s2">&quot;125C&quot;</span><span class="p">)</span>
<span class="n">critical</span> <span class="o">=</span> <span class="n">PartClass</span><span class="p">(</span><span class="s2">&quot;critical&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">10</span><span class="p">,</span> <span class="n">review_required</span><span class="o">=</span><span class="kc">True</span><span class="p">)</span>
<span class="n">commercial</span> <span class="o">=</span> <span class="n">PartClass</span><span class="p">(</span><span class="s2">&quot;commercial&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">3</span><span class="p">)</span>

<span class="c1"># Create net classes for different signal types.</span>
<span class="n">high_speed</span> <span class="o">=</span> <span class="n">NetClass</span><span class="p">(</span><span class="s2">&quot;high_speed&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">2</span><span class="p">,</span> <span class="n">width</span><span class="o">=</span><span class="s2">&quot;0.1mm&quot;</span><span class="p">,</span> <span class="n">impedance</span><span class="o">=</span><span class="s2">&quot;50ohm&quot;</span><span class="p">)</span>
<span class="n">clock_nets</span> <span class="o">=</span> <span class="n">NetClass</span><span class="p">(</span><span class="s2">&quot;clocks&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">3</span><span class="p">,</span> <span class="n">width</span><span class="o">=</span><span class="s2">&quot;0.08mm&quot;</span><span class="p">)</span>
<span class="n">power_nets</span> <span class="o">=</span> <span class="n">NetClass</span><span class="p">(</span><span class="s2">&quot;power_nets&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">4</span><span class="p">,</span> <span class="n">width</span><span class="o">=</span><span class="s2">&quot;0.5mm&quot;</span><span class="p">,</span> <span class="n">clearance</span><span class="o">=</span><span class="s2">&quot;0.3mm&quot;</span><span class="p">)</span>

<span class="c1"># Create parts and assign classes during instantiation or separately.</span>
<span class="n">resistor</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="s2">&quot;R&quot;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s2">&quot;1K&quot;</span><span class="p">,</span> <span class="n">partclasses</span><span class="o">=</span><span class="p">(</span><span class="n">passive_parts</span><span class="p">,</span><span class="n">commercial</span><span class="p">))</span>
<span class="n">vreg</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Regulator_Linear&quot;</span><span class="p">,</span> <span class="s2">&quot;AMS1117-3.3&quot;</span><span class="p">)</span>
<span class="n">vreg</span><span class="o">.</span><span class="n">partclasses</span> <span class="o">=</span> <span class="n">power_parts</span><span class="p">,</span> <span class="n">active_parts</span><span class="p">,</span> <span class="n">critical</span>

<span class="c1"># Create nets and assign classes.</span>
<span class="n">vcc_5v</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s2">&quot;VCC_5V&quot;</span><span class="p">,</span> <span class="n">netclasses</span><span class="o">=</span><span class="n">power_nets</span><span class="p">)</span>
<span class="n">data_bus</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s2">&quot;DATA&quot;</span><span class="p">,</span> <span class="mi">8</span><span class="p">,</span> <span class="n">netclasses</span><span class="o">=</span><span class="n">high_speed</span><span class="p">)</span>
<span class="n">data_bus</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span><span class="o">.</span><span class="n">netclasses</span> <span class="o">=</span> <span class="n">clock_nets</span>  <span class="c1"># Assign additional class to individual bus line</span>
</code></pre></div>

<h3 id="hierarchical-part-and-net-class-inheritance">Hierarchical Part and Net Class Inheritance</h3>
<p>Classes can be assigned at different levels of circuit hierarchy,
with parts and nets at lower levels inheriting classes from higher levels:</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>

<span class="c1"># Assign global part class to root level (applies to entire circuit)</span>
<span class="n">default_circuit</span><span class="o">.</span><span class="n">root</span><span class="o">.</span><span class="n">partclasses</span> <span class="o">=</span> <span class="n">PartClass</span><span class="p">(</span><span class="s2">&quot;global&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span> <span class="n">vendor</span><span class="o">=</span><span class="s2">&quot;TI&quot;</span><span class="p">)</span>

<span class="c1"># Create hierarchical design with class inheritance</span>
<span class="k">with</span> <span class="n">SubCircuit</span><span class="p">(</span><span class="s2">&quot;power_supply&quot;</span><span class="p">)</span> <span class="k">as</span> <span class="n">psu</span><span class="p">:</span>
    <span class="c1"># Power supply specific classes</span>
    <span class="n">psu</span><span class="o">.</span><span class="n">partclasses</span> <span class="o">=</span> <span class="n">PartClass</span><span class="p">(</span><span class="s2">&quot;psu_parts&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">1</span><span class="p">,</span> <span class="n">efficiency</span><span class="o">=</span><span class="s2">&quot;&gt;90%&quot;</span><span class="p">)</span>

    <span class="c1"># Components inherit both global and PSU classes</span>
    <span class="n">reg</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Regulator_Switching&quot;</span><span class="p">,</span> <span class="s2">&quot;LM2596T-ADJ&quot;</span><span class="p">)</span>
    <span class="n">cap</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="s2">&quot;C&quot;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s2">&quot;470uF&quot;</span><span class="p">)</span>

<span class="k">with</span> <span class="n">SubCircuit</span><span class="p">(</span><span class="s2">&quot;analog_frontend&quot;</span><span class="p">)</span> <span class="k">as</span> <span class="n">afe</span><span class="p">:</span>
    <span class="c1"># Analog-specific classes</span>
    <span class="n">afe</span><span class="o">.</span><span class="n">partclasses</span> <span class="o">=</span> <span class="n">PartClass</span><span class="p">(</span><span class="s2">&quot;precision&quot;</span><span class="p">,</span> <span class="n">priority</span><span class="o">=</span><span class="mi">1</span><span class="p">,</span> <span class="n">tolerance</span><span class="o">=</span><span class="s2">&quot;0.1%&quot;</span><span class="p">)</span>

    <span class="k">with</span> <span class="n">SubCircuit</span><span class="p">(</span><span class="s2">&quot;amplifier_stage&quot;</span><span class="p">)</span> <span class="k">as</span> <span class="n">amp</span><span class="p">:</span>
        <span class="c1"># Nested hierarchy - inherits both global and precision part classes</span>
        <span class="n">opamp</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Amplifier_Operational&quot;</span><span class="p">,</span> <span class="s2">&quot;OPA690xD&quot;</span><span class="p">)</span>

<span class="c1"># Access circuit-wide class collections</span>
<span class="n">all_part_classes</span> <span class="o">=</span> <span class="n">default_circuit</span><span class="o">.</span><span class="n">partclasses</span>
<span class="nb">print</span><span class="p">(</span><span class="sa">f</span><span class="s2">&quot;</span><span class="si">{</span><span class="n">all_part_classes</span><span class="si">=}</span><span class="s2">&quot;</span><span class="p">)</span>
</code></pre></div>

<h2 id="part-fields">Part Fields</h2>
<p>Parts typically have <em>fields</em> that store additional information such as
manufacturer identifiers.
Every <code>Part</code> object stores this information in a dictionary called <code>fields</code>:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt; lm35 = Part(&#39;Sensor_Temperature&#39;, &#39;LM35-D&#39;)
&gt;&gt; lm35.fields

{&#39;F0&#39;: &#39;U&#39;,
 &#39;F1&#39;: &#39;LM35-D&#39;,
 &#39;F2&#39;: &#39;Package_SO:SOIC-8_3.9x4.9mm_P1.27mm&#39;,
 &#39;F3&#39;: &#39;&#39;}

&gt;&gt;&gt; lm35.fields[&#39;F1&#39;]

&#39;LM35-D&#39;
</code></pre></div>

<p>Key/value pairs stored in <code>fields</code> will get exported in the netlist file when it is generated,
so this is the way to pass data to downstream tools like <code>PCBNEW</code>.</p>
<p>New fields can be added just by adding new keys and values to the <code>fields</code> dictionary.
Once a field has been added to the dictionary, it can also be accessed and changed
as a part attribute:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; lm35.fields[&#39;new_field&#39;] = &#39;new value&#39;
&gt;&gt;&gt; lm35.new_field

&#39;new value&#39;

&gt;&gt;&gt; lm35.new_field = &#39;another new value&#39;
&gt;&gt;&gt; lm35.new_field

&#39;another new value&#39;
</code></pre></div>

<h2 id="hierarchy">Hierarchy</h2>
<p>SKiDL supports hierarchical design using decorated functions that return interfaces,
subclassed modules with I/O attributes, and context-based hierarchy.
You can combine and nest these approaches as needed. For example, use subclassed modules for complex reusable blocks like motor drivers, decorated functions for parameterizable filters, and context-based hierarchy for organizing collections of parts like bypass capacitors.</p>
<h3 id="method-1-subcircuit-decorator-with-interface-return">Method 1: SubCircuit Decorator with Interface Return</h3>
<p>This approach uses the <code>@SubCircuit</code> decorator on functions that return an <code>Interface</code> object containing the subcircuit's I/O connections.</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>

<span class="nd">@SubCircuit</span>
<span class="k">def</span> <span class="nf">voltage_regulator</span><span class="p">():</span>
<span class="w">    </span><span class="sd">&quot;&quot;&quot;3.3V linear voltage regulator module.&quot;&quot;&quot;</span>

    <span class="c1"># Create voltage regulator and filter capacitors</span>
    <span class="n">reg</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Regulator_Linear&#39;</span><span class="p">,</span> <span class="s1">&#39;AMS1117-3.3&#39;</span><span class="p">)</span>
    <span class="n">c_in</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;C&#39;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s1">&#39;100nF&#39;</span><span class="p">)</span>
    <span class="n">c_out</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;C&#39;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s1">&#39;10uF&#39;</span><span class="p">)</span>

    <span class="c1"># Attach input/output filter capacitors.</span>
    <span class="n">reg</span><span class="p">[</span><span class="s1">&#39;VI&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">c_in</span> <span class="o">&amp;</span> <span class="n">reg</span><span class="p">[</span><span class="s1">&#39;GND&#39;</span><span class="p">]</span>
    <span class="n">reg</span><span class="p">[</span><span class="s1">&#39;VO&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">c_out</span> <span class="o">&amp;</span> <span class="n">reg</span><span class="p">[</span><span class="s1">&#39;GND&#39;</span><span class="p">]</span>

    <span class="c1"># Return interface connections</span>
    <span class="k">return</span> <span class="n">Interface</span><span class="p">(</span>
        <span class="n">vin</span><span class="o">=</span><span class="n">reg</span><span class="p">[</span><span class="s1">&#39;VI&#39;</span><span class="p">],</span>      <span class="c1"># Unregulated supply voltage</span>
        <span class="n">vout</span><span class="o">=</span><span class="n">reg</span><span class="p">[</span><span class="s1">&#39;VO&#39;</span><span class="p">],</span>     <span class="c1"># Regulated output voltage</span>
        <span class="n">gnd</span><span class="o">=</span><span class="n">reg</span><span class="p">[</span><span class="s1">&#39;GND&#39;</span><span class="p">]</span>      <span class="c1"># Ground connection</span>
        <span class="p">)</span>

<span class="nd">@subcircuit</span>
<span class="k">def</span> <span class="nf">motor_driver</span><span class="p">():</span>
<span class="w">    </span><span class="sd">&quot;&quot;&quot;H-bridge motor driver module.&quot;&quot;&quot;</span>

    <span class="c1"># Create MOSFETs for H-bridge</span>
    <span class="n">q1</span><span class="p">,</span> <span class="n">q2</span><span class="p">,</span> <span class="n">q3</span><span class="p">,</span> <span class="n">q4</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Transistor_FET&#39;</span><span class="p">,</span> <span class="s1">&#39;Q_NMOS_GSD&#39;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)(</span><span class="mi">4</span><span class="p">)</span>

    <span class="c1"># Define local nets for power and motor connections</span>
    <span class="n">vcc</span><span class="p">,</span> <span class="n">gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(),</span> <span class="n">Net</span><span class="p">()</span>          <span class="c1"># Motor supply voltages</span>
    <span class="n">motor_a</span><span class="p">,</span> <span class="n">motor_b</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(),</span> <span class="n">Net</span><span class="p">()</span>  <span class="c1"># Motor terminals</span>

    <span class="c1"># Build H-bridge topology</span>
    <span class="n">vcc</span> <span class="o">&amp;</span> <span class="n">q1</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">motor_a</span> <span class="o">&amp;</span> <span class="n">q2</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">gnd</span>
    <span class="n">vcc</span> <span class="o">&amp;</span> <span class="n">q3</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">motor_b</span> <span class="o">&amp;</span> <span class="n">q4</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">gnd</span>

    <span class="c1"># Return interface connections</span>
    <span class="k">return</span> <span class="n">Interface</span><span class="p">(</span>
        <span class="n">vcc</span><span class="o">=</span><span class="n">vcc</span><span class="p">,</span>             <span class="c1"># Motor supply voltage</span>
        <span class="n">gnd</span><span class="o">=</span><span class="n">gnd</span><span class="p">,</span>             <span class="c1"># Ground</span>
        <span class="n">motor_a</span><span class="o">=</span><span class="n">motor_a</span><span class="p">,</span>     <span class="c1"># Motor terminal A</span>
        <span class="n">motor_b</span><span class="o">=</span><span class="n">motor_b</span><span class="p">,</span>     <span class="c1"># Motor terminal B</span>
        <span class="n">ctrl1</span><span class="o">=</span><span class="n">q1</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">],</span>       <span class="c1"># Control signal 1</span>
        <span class="n">ctrl2</span><span class="o">=</span><span class="n">q2</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">],</span>       <span class="c1"># Control signal 2</span>
        <span class="n">ctrl3</span><span class="o">=</span><span class="n">q3</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">],</span>       <span class="c1"># Control signal 3</span>
        <span class="n">ctrl4</span><span class="o">=</span><span class="n">q4</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">]</span>        <span class="c1"># Control signal 4</span>
        <span class="p">)</span>

<span class="c1"># Instantiate subcircuit modules</span>
<span class="n">regulator</span> <span class="o">=</span> <span class="n">voltage_regulator</span><span class="p">()</span>
<span class="n">motor_drv</span> <span class="o">=</span> <span class="n">motor_driver</span><span class="p">()</span>

<span class="c1"># Instantiate a DC motor</span>
<span class="n">motor</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Motor&quot;</span><span class="p">,</span> <span class="s2">&quot;Motor_DC&quot;</span><span class="p">)</span>

<span class="c1"># Create nets for power distribution</span>
<span class="n">power_12v</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;12V_IN&#39;</span><span class="p">)</span>
<span class="n">power_3v3</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;3V3&#39;</span><span class="p">)</span>
<span class="n">system_gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;GND&#39;</span><span class="p">)</span>

<span class="c1"># Connect power distribution to subcircuit module interfaces</span>
<span class="n">power_12v</span> <span class="o">+=</span> <span class="n">regulator</span><span class="o">.</span><span class="n">vin</span><span class="p">,</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">vcc</span>
<span class="n">power_3v3</span> <span class="o">+=</span> <span class="n">regulator</span><span class="o">.</span><span class="n">vout</span>
<span class="n">system_gnd</span> <span class="o">+=</span> <span class="n">regulator</span><span class="o">.</span><span class="n">gnd</span><span class="p">,</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">gnd</span>

<span class="c1"># Connect control signals to microcontroller</span>
<span class="n">mcu</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;MCU_ST_STM32F1&#39;</span><span class="p">,</span> <span class="s1">&#39;STM32F103C8Tx&#39;</span><span class="p">)</span>
<span class="n">mcu</span><span class="p">[</span><span class="s1">&#39;PA0,PA1,PA2,PA3&#39;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">ctrl1</span><span class="p">,</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">ctrl2</span><span class="p">,</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">ctrl3</span><span class="p">,</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">ctrl4</span>

<span class="c1"># Connect motor</span>
<span class="n">motor</span><span class="p">[</span><span class="s2">&quot;+&quot;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">motor_a</span>
<span class="n">motor</span><span class="p">[</span><span class="s2">&quot;-&quot;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">motor_b</span>

<span class="n">generate_netlist</span><span class="p">()</span>
</code></pre></div>

<h3 id="method-2-subcircuit-subclassing-with-io-attributes">Method 2: SubCircuit Subclassing with I/O Attributes</h3>
<p>The object-oriented approach involves subclassing <code>SubCircuit</code> to create modules with I/O attributes.</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>

<span class="k">class</span> <span class="nc">VoltageRegulator</span><span class="p">(</span><span class="n">SubCircuit</span><span class="p">):</span>
<span class="w">    </span><span class="sd">&quot;&quot;&quot;3.3V linear voltage regulator module.&quot;&quot;&quot;</span>

    <span class="k">def</span> <span class="fm">__init__</span><span class="p">(</span><span class="bp">self</span><span class="p">):</span>
        <span class="c1"># Initialize this subcircuit. DO NOT USE super().__init__()!</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">initialize</span><span class="p">()</span>

        <span class="c1"># Create voltage regulator and filter capacitors</span>
        <span class="n">reg</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Regulator_Linear&#39;</span><span class="p">,</span> <span class="s1">&#39;AMS1117-3.3&#39;</span><span class="p">)</span>
        <span class="n">c_in</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;C&#39;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s1">&#39;100nF&#39;</span><span class="p">)</span>
        <span class="n">c_out</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;C&#39;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s1">&#39;10uF&#39;</span><span class="p">)</span>

        <span class="c1"># Define I/O attributes</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">vin</span> <span class="o">=</span> <span class="n">reg</span><span class="p">[</span><span class="s1">&#39;VI&#39;</span><span class="p">]</span>      <span class="c1"># Voltage input</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">vout</span> <span class="o">=</span> <span class="n">reg</span><span class="p">[</span><span class="s1">&#39;VO&#39;</span><span class="p">]</span>     <span class="c1"># Regulated output</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">gnd</span> <span class="o">=</span> <span class="n">reg</span><span class="p">[</span><span class="s1">&#39;GND&#39;</span><span class="p">]</span>     <span class="c1"># Ground connection</span>

        <span class="c1"># Attach input/output filter capacitors</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">vin</span> <span class="o">&amp;</span> <span class="n">c_in</span> <span class="o">&amp;</span> <span class="bp">self</span><span class="o">.</span><span class="n">gnd</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">vout</span> <span class="o">&amp;</span> <span class="n">c_out</span> <span class="o">&amp;</span> <span class="bp">self</span><span class="o">.</span><span class="n">gnd</span>

        <span class="c1"># Finalize the creation of the subcircuit</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">finalize</span><span class="p">()</span>

<span class="k">class</span> <span class="nc">MotorDriver</span><span class="p">(</span><span class="n">SubCircuit</span><span class="p">):</span>
<span class="w">    </span><span class="sd">&quot;&quot;&quot;H-bridge motor driver module.&quot;&quot;&quot;</span>

    <span class="k">def</span> <span class="fm">__init__</span><span class="p">(</span><span class="bp">self</span><span class="p">):</span>
        <span class="c1"># Initialize this subcircuit. DO NOT USE super().__init__()!</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">initialize</span><span class="p">()</span>

        <span class="c1"># Create MOSFETS for H-bridge</span>
        <span class="n">q1</span><span class="p">,</span> <span class="n">q2</span><span class="p">,</span> <span class="n">q3</span><span class="p">,</span> <span class="n">q4</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Transistor_FET&#39;</span><span class="p">,</span> <span class="s1">&#39;Q_NMOS_GSD&#39;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)(</span><span class="mi">4</span><span class="p">)</span>

        <span class="c1"># Define I/O attributes</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">vcc</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>          <span class="c1"># Motor supply voltage</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>          <span class="c1"># Ground</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">motor_a</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>      <span class="c1"># Motor terminal A</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">motor_b</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>      <span class="c1"># Motor terminal B</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">ctrl1</span> <span class="o">=</span> <span class="n">q1</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">]</span>      <span class="c1"># Control signal 1</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">ctrl2</span> <span class="o">=</span> <span class="n">q2</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">]</span>      <span class="c1"># Control signal 2</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">ctrl3</span> <span class="o">=</span> <span class="n">q3</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">]</span>      <span class="c1"># Control signal 3</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">ctrl4</span> <span class="o">=</span> <span class="n">q4</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">]</span>      <span class="c1"># Control signal 4</span>

        <span class="c1"># Build H-bridge topology</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">vcc</span> <span class="o">&amp;</span> <span class="n">q1</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="bp">self</span><span class="o">.</span><span class="n">motor_a</span> <span class="o">&amp;</span> <span class="n">q2</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="bp">self</span><span class="o">.</span><span class="n">gnd</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">vcc</span> <span class="o">&amp;</span> <span class="n">q3</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="bp">self</span><span class="o">.</span><span class="n">motor_b</span> <span class="o">&amp;</span> <span class="n">q4</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="bp">self</span><span class="o">.</span><span class="n">gnd</span>

        <span class="c1"># Finalize the creation of the subcircuit</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">finalize</span><span class="p">()</span>

<span class="c1"># Instantiate subcircuit modules</span>
<span class="n">regulator</span> <span class="o">=</span> <span class="n">VoltageRegulator</span><span class="p">()</span>
<span class="n">motor_drv</span> <span class="o">=</span> <span class="n">MotorDriver</span><span class="p">()</span>

<span class="c1"># Instantiate a DC motor</span>
<span class="n">motor</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Motor&quot;</span><span class="p">,</span> <span class="s2">&quot;Motor_DC&quot;</span><span class="p">)</span>

<span class="c1"># Create nets for power distribution</span>
<span class="n">power_12v</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;12V_IN&#39;</span><span class="p">)</span>
<span class="n">power_3v3</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;3V3&#39;</span><span class="p">)</span>
<span class="n">system_gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;GND&#39;</span><span class="p">)</span>

<span class="c1"># Connect power distribution to subcircuit modules</span>
<span class="n">power_12v</span> <span class="o">+=</span> <span class="n">regulator</span><span class="o">.</span><span class="n">vin</span><span class="p">,</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">vcc</span>
<span class="n">power_3v3</span> <span class="o">+=</span> <span class="n">regulator</span><span class="o">.</span><span class="n">vout</span>
<span class="n">system_gnd</span> <span class="o">+=</span> <span class="n">regulator</span><span class="o">.</span><span class="n">gnd</span><span class="p">,</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">gnd</span>

<span class="c1"># Connect control signals using module attributes</span>
<span class="n">mcu</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;MCU_ST_STM32F1&#39;</span><span class="p">,</span> <span class="s1">&#39;STM32F103C8Tx&#39;</span><span class="p">)</span>
<span class="n">mcu</span><span class="p">[</span><span class="s1">&#39;PA0,PA1,PA2,PA3&#39;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">ctrl1</span><span class="p">,</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">ctrl2</span><span class="p">,</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">ctrl3</span><span class="p">,</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">ctrl4</span>

<span class="c1"># Connect motor</span>
<span class="n">motor</span><span class="p">[</span><span class="s2">&quot;+&quot;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">motor_a</span>
<span class="n">motor</span><span class="p">[</span><span class="s2">&quot;-&quot;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">motor_drv</span><span class="o">.</span><span class="n">motor_b</span>

<span class="n">generate_netlist</span><span class="p">()</span>
</code></pre></div>

<h3 id="method-3-subcircuit-context-manager">Method 3: SubCircuit Context Manager</h3>
<p>The final approach uses <code>SubCircuit</code> as a context manager to create hierarchical groupings without defining functions or classes.
This allows grouping of components into logical sections, but unlike the other approaches, re-using a group is not possible.</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>

<span class="c1"># Create nets for power distribution</span>
<span class="n">power_12v</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;12V_IN&#39;</span><span class="p">)</span>
<span class="n">power_3v3</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;3V3&#39;</span><span class="p">)</span>
<span class="n">system_gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;GND&#39;</span><span class="p">)</span>

<span class="k">with</span> <span class="n">SubCircuit</span><span class="p">(</span><span class="s1">&#39;voltage_regulator&#39;</span><span class="p">)</span> <span class="k">as</span> <span class="n">voltage_regulator</span><span class="p">:</span>
<span class="w">    </span><span class="sd">&quot;&quot;&quot;3.3V linear voltage regulator.&quot;&quot;&quot;</span>

    <span class="c1"># Create voltage regulator and filter capacitors</span>
    <span class="n">reg</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Regulator_Linear&#39;</span><span class="p">,</span> <span class="s1">&#39;AMS1117-3.3&#39;</span><span class="p">)</span>
    <span class="n">c_in</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;C&#39;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s1">&#39;100nF&#39;</span><span class="p">)</span>
    <span class="n">c_out</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;C&#39;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s1">&#39;10uF&#39;</span><span class="p">)</span>

    <span class="c1"># Attach power in/out connections and input/output filter capacitors</span>
    <span class="n">power_12v</span> <span class="o">&amp;</span> <span class="n">reg</span><span class="p">[</span><span class="s1">&#39;VI&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">c_in</span> <span class="o">&amp;</span> <span class="n">system_gnd</span>
    <span class="n">power_3v3</span> <span class="o">&amp;</span> <span class="n">reg</span><span class="p">[</span><span class="s1">&#39;VO&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">c_out</span> <span class="o">&amp;</span> <span class="n">system_gnd</span>

<span class="k">with</span> <span class="n">SubCircuit</span><span class="p">(</span><span class="s1">&#39;motor_driver&#39;</span><span class="p">)</span> <span class="k">as</span> <span class="n">motor_driver</span><span class="p">:</span>
<span class="w">    </span><span class="sd">&quot;&quot;&quot;H-bridge motor driver.&quot;&quot;&quot;</span>

    <span class="c1"># Create MOSFETs for H-bridge</span>
    <span class="n">q1</span><span class="p">,</span> <span class="n">q2</span><span class="p">,</span> <span class="n">q3</span><span class="p">,</span> <span class="n">q4</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Transistor_FET&#39;</span><span class="p">,</span> <span class="s1">&#39;Q_NMOS_GSD&#39;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)(</span><span class="mi">4</span><span class="p">)</span>

    <span class="c1"># Define local nets for connecting motor</span>
    <span class="n">motor_a</span><span class="p">,</span> <span class="n">motor_b</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(),</span> <span class="n">Net</span><span class="p">()</span>  <span class="c1"># Motor terminals</span>

    <span class="c1"># Build H-bridge topology</span>
    <span class="n">power_12v</span> <span class="o">&amp;</span> <span class="n">q1</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">motor_a</span> <span class="o">&amp;</span> <span class="n">q2</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">system_gnd</span>
    <span class="n">power_12v</span> <span class="o">&amp;</span> <span class="n">q3</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">motor_b</span> <span class="o">&amp;</span> <span class="n">q4</span><span class="p">[</span><span class="s1">&#39;D,S&#39;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">system_gnd</span>

    <span class="c1"># H-bridge control pins.</span>
    <span class="n">motor_ctrl1</span><span class="o">=</span><span class="n">q1</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">]</span>
    <span class="n">motor_ctrl2</span><span class="o">=</span><span class="n">q2</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">]</span>
    <span class="n">motor_ctrl3</span><span class="o">=</span><span class="n">q3</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">]</span>
    <span class="n">motor_ctrl4</span><span class="o">=</span><span class="n">q4</span><span class="p">[</span><span class="s1">&#39;G&#39;</span><span class="p">]</span>

<span class="c1"># Instantiate a DC motor</span>
<span class="n">motor</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Motor&quot;</span><span class="p">,</span> <span class="s2">&quot;Motor_DC&quot;</span><span class="p">)</span>

<span class="c1"># Connect control signals to microcontroller</span>
<span class="n">mcu</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;MCU_ST_STM32F1&#39;</span><span class="p">,</span> <span class="s1">&#39;STM32F103C8Tx&#39;</span><span class="p">)</span>
<span class="n">mcu</span><span class="p">[</span><span class="s1">&#39;PA0,PA1,PA2,PA3&#39;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">motor_ctrl1</span><span class="p">,</span> <span class="n">motor_ctrl2</span><span class="p">,</span> <span class="n">motor_ctrl3</span><span class="p">,</span> <span class="n">motor_ctrl4</span>

<span class="c1"># Connect motor</span>
<span class="n">motor</span><span class="p">[</span><span class="s2">&quot;+&quot;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">motor_a</span>
<span class="n">motor</span><span class="p">[</span><span class="s2">&quot;-&quot;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">motor_b</span>

<span class="n">generate_netlist</span><span class="p">()</span>
</code></pre></div>

<h2 id="libraries">Libraries</h2>
<p>As you've already seen, SKiDL gets its parts from <em>part libraries</em>.
By default, SKiDL finds the libraries provided by KiCad (using the <code>KICAD_SYMBOL_DIR</code>
environment variable), so if that's all you need then you're all set.</p>
<p>Currently, SKiDL supports the library formats for the following ECAD tools:</p>
<ul>
<li><code>KICAD5</code>: Schematic part libraries for KiCad version 5.</li>
<li><code>KICAD6</code>: Schematic part libraries for KiCad version 6.</li>
<li><code>KICAD7</code>: Schematic part libraries for KiCad version 7.</li>
<li><code>KICAD8</code>: Schematic part libraries for KiCad version 8.</li>
<li><code>KICAD9</code>: Schematic part libraries for KiCad version 9.</li>
<li><code>KICAD</code>: Generic KiCad schematic part libraries that currently mirrors <code>KICAD9</code>.</li>
<li><code>SKIDL</code>: Schematic parts stored as SKiDL/Python modules.</li>
</ul>
<p>You may set the default library format you want to use in your SKiDL script like so:</p>
<div class="highlight"><pre><span></span><code><span class="n">set_default_tool</span><span class="p">(</span><span class="n">KICAD</span><span class="p">)</span>  <span class="c1"># KiCad is the default library format.</span>
<span class="n">set_default_tool</span><span class="p">(</span><span class="n">SKIDL</span><span class="p">)</span>  <span class="c1"># Now SKiDL is the default library format.</span>
</code></pre></div>

<p>You can select the directories where SKiDL looks for parts or footprints using the 
<code>lib_search_paths</code> or <code>footprint_search_paths</code> dictionaries, respectively:</p>
<div class="highlight"><pre><span></span><code><span class="n">lib_search_paths</span><span class="p">[</span><span class="n">SKIDL</span><span class="p">]</span> <span class="o">=</span> <span class="p">[</span><span class="s1">&#39;.&#39;</span><span class="p">,</span> <span class="s1">&#39;..&#39;</span><span class="p">,</span> <span class="s1">&#39;C:</span><span class="se">\\</span><span class="s1">temp&#39;</span><span class="p">]</span>
<span class="n">lib_search_paths</span><span class="p">[</span><span class="n">KICAD</span><span class="p">]</span><span class="o">.</span><span class="n">append</span><span class="p">(</span><span class="s1">&#39;C:</span><span class="se">\\</span><span class="s1">my</span><span class="se">\\</span><span class="s1">kicad</span><span class="se">\\</span><span class="s1">libs&#39;</span><span class="p">)</span>
</code></pre></div>

<p>You may also access a library stored in an online repository just by placing its
URL in the list of libraries:</p>
<div class="highlight"><pre><span></span><code><span class="n">lib_search_paths</span><span class="p">[</span><span class="n">KICAD</span><span class="p">]</span><span class="o">.</span><span class="n">append</span><span class="p">(</span><span class="s1">&#39;https://gitlab.com/kicad/libraries/kicad-symbols/-/raw/master&#39;</span><span class="p">)</span>
</code></pre></div>

<p>You can also bypass <code>lib_search_paths</code> and access a part library directly by
specifying the full path or URL to the library file:</p>
<div class="highlight"><pre><span></span><code><span class="n">resistor</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;C:</span><span class="se">\\</span><span class="s1">my</span><span class="se">\\</span><span class="s1">kicad</span><span class="se">\\</span><span class="s1">libs</span><span class="se">\\</span><span class="s1">my_lib.kicad_sym&#39;</span><span class="p">,</span> <span class="s1">&#39;R&#39;</span><span class="p">)</span>
</code></pre></div>

<p>Opening large libraries can cause a significant delay as the part descriptions are parsed
into the internal <code>SchLib</code> data structure.
To speed up the process, libraries are cached after parsing so subsequent accesses
during a session will be fast.</p>
<p>SKiDL will also <a href="https://docs.python.org/3/library/pickle.html">pickle</a> any local libraries
(but not those in online repositories) to disk so they can be reloaded quickly in future sessions.
If the original library file is modified, SKiDL will re-parse it and update the pickled file.
By default, pickled library files are stored in the <code>lib_pickle_dir</code> subdirectory of the current directory.
You can change the location of the pickled library files by setting the <code>pickle_dir</code> entry in
the <a href="#configuration-file">configuration file</a>.</p>
<p>You can convert a KiCad library into the SKiDL format by exporting it:</p>
<div class="highlight"><pre><span></span><code><span class="n">kicad_lib</span> <span class="o">=</span> <span class="n">SchLib</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="n">tool</span><span class="o">=</span><span class="n">KICAD</span><span class="p">)</span>       <span class="c1"># Open a KiCad library.</span>
<span class="n">kicad_lib</span><span class="o">.</span><span class="n">export</span><span class="p">(</span><span class="s1">&#39;my_skidl_lib&#39;</span><span class="p">)</span>               <span class="c1"># Export it into a file in SKiDL format.</span>
<span class="n">skidl_lib</span> <span class="o">=</span> <span class="n">SchLib</span><span class="p">(</span><span class="s1">&#39;my_skidl_lib&#39;</span><span class="p">,</span> <span class="n">tool</span><span class="o">=</span><span class="n">SKIDL</span><span class="p">)</span> <span class="c1"># Create a SKiDL library object from the export file.</span>
<span class="k">if</span> <span class="nb">len</span><span class="p">(</span><span class="n">skidl_lib</span><span class="p">)</span> <span class="o">==</span> <span class="nb">len</span><span class="p">(</span><span class="n">kicad_lib</span><span class="p">):</span>
    <span class="nb">print</span><span class="p">(</span><span class="s1">&#39;As expected, both libraries have the same number of parts!&#39;</span><span class="p">)</span>
<span class="k">else</span><span class="p">:</span>
    <span class="nb">print</span><span class="p">(</span><span class="s1">&#39;Something went wrong!&#39;</span><span class="p">)</span>
<span class="n">diode</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="n">skidl_lib</span><span class="p">,</span> <span class="s1">&#39;D&#39;</span><span class="p">)</span>                   <span class="c1"># Instantiate a diode from the SKiDL library.</span>
</code></pre></div>

<p>You can make ad-hoc libraries just by creating an empty <code>SchLib</code> object and adding
Part templates to it:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_lib</span> <span class="o">=</span> <span class="n">SchLib</span><span class="p">(</span><span class="n">name</span><span class="o">=</span><span class="s1">&#39;my_lib&#39;</span><span class="p">)</span>                <span class="c1"># Create an empty library object.</span>
<span class="n">my_lib</span> <span class="o">+=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;R&#39;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)</span>  <span class="c1"># Add a part template to the library.</span>
</code></pre></div>

<p>Always create a part intended for a library as a template so it isn't inadvertently
added to the circuit netlist.</p>
<p>SKiDL will also create a library of all the parts used in your design whenever
you call the <code>generate_netlist()</code> function.
For example, if your SKiDL script is named <code>my_design.py</code>, then the parts instantiated
in that script will be stored as a SKiDL library in the file <code>my_design_sklib.py</code>.
This can be useful if you're sending the design to someone who may not have all
the libraries you do.
Just send them <code>my_design.py</code> and <code>my_design_sklib.py</code> and any parts not found
when they run the script will be fetched from the backup parts in the library.</p>
<h2 id="doodads">Doodads</h2>
<p>SKiDL has a few features that don't fit into any other
category. Here they are.</p>
<h3 id="no-connects">No Connects</h3>
<p>Sometimes you will use a part, but you won't use every pin.
The ERC will complain about those unconnected pins:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;) 
&gt;&gt;&gt; ERC()
ERC WARNING: Unconnected pin: BIDIRECTIONAL pin 1/GP0 of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: POWER-IN pin 2/VSS of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: BIDIRECTIONAL pin 3/GP1 of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: BIDIRECTIONAL pin 4/GP2 of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: POWER-IN pin 5/VDD of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: INPUT pin 6/GP3 of PIC10F220-IOT/U1.

6 warnings found during ERC.
0 errors found during ERC.
</code></pre></div>

<p>If you have pins that you intentionally want to leave unconnected, then
attach them to the special-purpose <code>NC</code> (no-connect) net and the warnings will
be supressed:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10[1,3,4] += NC
&gt;&gt;&gt; ERC()
ERC WARNING: Unconnected pin: POWER-IN pin 2/VSS of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: POWER-IN pin 5/VDD of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: INPUT pin 6/GP3 of PIC10F220-IOT/U1.

3 warnings found during ERC.
0 errors found during ERC.
</code></pre></div>

<p>In fact, if you have a part with many pins that are not going to be used,
you can start off by attaching all the pins to the <code>NC</code> net.
After that, you may attach the pins you're using to normal nets and they
will be removed from the <code>NC</code> net:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_part</span><span class="p">[:]</span> <span class="o">+=</span> <span class="n">NC</span>  <span class="c1"># Connect every pin to NC net.</span>
<span class="o">...</span>
<span class="n">my_part</span><span class="p">[</span><span class="mi">5</span><span class="p">]</span> <span class="o">+=</span> <span class="n">Net</span><span class="p">()</span>  <span class="c1"># Pin 5 is no longer unconnected.</span>
</code></pre></div>

<p>The <code>NC</code> net is the only net for which this happens.
For all other nets, connecting two or more nets to the same pin
merges those nets and all the pins on them together.</p>
<h3 id="net-and-pin-drive-levels">Net and Pin Drive Levels</h3>
<p>Certain parts have power pins that are required to be driven by
a power supply net or else ERC warnings ensue.
This condition is usually satisfied if the power pins are driven by
the output of another part like a voltage regulator.
But if the regulator output passes through something like a 
ferrite bead (to remove noise), then the filtered signal
is no longer a supply net and an ERC warning is issued.</p>
<p>In order to satisfy the ERC, the drive strength of a net can be set manually
using its <code>drive</code> attribute. As a simple example, consider connecting
a net to the power supply input of a processor and then running
the ERC:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;) 
&gt;&gt;&gt; a = Net()
&gt;&gt;&gt; pic10[&#39;VDD&#39;] += a
&gt;&gt;&gt; ERC()
...
ERC WARNING: Insufficient drive current on net N$1 for pin POWER-IN pin 5/VDD of PIC10F220-IOT/U1
...
</code></pre></div>

<p>To fix this issue, change the <code>drive</code> attribute of the net:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10 = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;)
&gt;&gt;&gt; a = Net()
&gt;&gt;&gt; pic10[&#39;VDD&#39;] += a
&gt;&gt;&gt; a.drive = POWER
&gt;&gt;&gt; ERC()
...
(Insufficient drive warning is no longer present.)
...
</code></pre></div>

<p>You can set the <code>drive</code> attribute at any time to any defined level, but <code>POWER</code>
is probably the only setting you'll use.
For any net you create that supplies power to devices in your circuit,
you should probably set its <code>drive</code> attribute to <code>POWER</code>.
This is equivalent to attaching power flags to nets in some ECAD packages like KiCad.</p>
<p>You may also set the <code>drive</code> attribute of part pins to override their default drive level.
This can be useful when you are using an output pin of a part to power
another part.</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; pic10_a = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;)
&gt;&gt;&gt; pic10_b = Part(&#39;MCU_Microchip_PIC10&#39;, &#39;pic10f220-iot&#39;)
&gt;&gt;&gt; pic10_b[&#39;VDD&#39;] += pic10_a[1]  # Power pic10_b from output pin of pic10_a.
&gt;&gt;&gt; ERC()
ERC WARNING: Insufficient drive current on net N$1 for pin POWER-IN pin 5/VDD of PIC10F220-IOT/U2
<span class="k">...</span> (additional unconnected pin warnings) ...

&gt;&gt;&gt; pic10_a[1].drive = POWER  # Change drive level of pic10_a output pin.
&gt;&gt;&gt; ERC()
<span class="k">...</span> (Insufficient drive warning is gone.) ...
</code></pre></div>

<h3 id="pin-net-bus-equivalencies">Pin, Net, Bus Equivalencies</h3>
<p>Pins, nets, and buses can all be connected to one another in a number of ways.
In order to make them as interchangeable as possible, some additional functions
are defined for each object:</p>
<p><strong><code>__bool__</code> and <code>__nonzero__</code></strong>:
    Each object will return <code>True</code> when used in a boolean operation.
    This can be useful when trying to select an active connection from a set of
    candidates using the <code>or</code> operator:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">a</span><span class="w"> </span><span class="p">=</span><span class="w"> </span><span class="nx">Net</span><span class="p">(</span><span class="sc">&#39;A&#39;</span><span class="p">)</span>
<span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">b</span><span class="w"> </span><span class="p">=</span><span class="w"> </span><span class="nx">Bus</span><span class="p">(</span><span class="sc">&#39;B&#39;</span><span class="p">,</span><span class="w"> </span><span class="mi">8</span><span class="p">)</span>
<span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">c</span><span class="w"> </span><span class="p">=</span><span class="w"> </span><span class="nx">Pin</span><span class="p">()</span>
<span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">d</span><span class="w"> </span><span class="p">=</span><span class="w"> </span><span class="nx">a</span><span class="w"> </span><span class="k">or</span><span class="w"> </span><span class="nx">b</span><span class="w"> </span><span class="k">or</span><span class="w"> </span><span class="nx">c</span>
<span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="nx">d</span>
<span class="nx">A</span><span class="p">:</span>
<span class="o">&gt;&gt;</span><span class="p">&gt;</span><span class="w"> </span><span class="k">type</span><span class="p">(</span><span class="nx">d</span><span class="p">)</span>
<span class="p">&lt;</span><span class="kd">class</span><span class="w"> </span><span class="err">&#39;</span><span class="nx">skidl</span><span class="p">.</span><span class="nx">Net</span><span class="p">.</span><span class="nx">Net</span><span class="err">&#39;</span><span class="p">&gt;</span>
</code></pre></div>

<p><strong>Indexing</strong>:
    Normally, indices can only be used with a Bus object to select one or more bus lines.
    But <code>Pin</code> and <code>Net</code> objects can also be indexed as long as the index evaluates to zero:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">a</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">Net</span><span class="p">(</span><span class="s1">&#39;A&#39;</span><span class="p">)</span>
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">c</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">Pin</span><span class="p">()</span>
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">a</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="n">c</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
<span class="n">WARNING</span><span class="p">:</span><span class="w"> </span><span class="n">Attaching</span><span class="w"> </span><span class="n">non</span><span class="o">-</span><span class="n">part</span><span class="w"> </span><span class="n">Pin</span><span class="w">  </span><span class="n">to</span><span class="w"> </span><span class="n">a</span><span class="w"> </span><span class="n">Net</span><span class="w"> </span><span class="n">A</span><span class="o">.</span>
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">a</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="n">c</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span>
<span class="n">ERROR</span><span class="p">:</span><span class="w"> </span><span class="n">Can</span><span class="s1">&#39;t use a non-zero index for a pin.</span>
<span class="n">Traceback</span><span class="w"> </span><span class="p">(</span><span class="n">most</span><span class="w"> </span><span class="n">recent</span><span class="w"> </span><span class="n">call</span><span class="w"> </span><span class="n">last</span><span class="p">):</span>
<span class="w">  </span><span class="n">File</span><span class="w"> </span><span class="s2">&quot;&lt;stdin&gt;&quot;</span><span class="p">,</span><span class="w"> </span><span class="n">line</span><span class="w"> </span><span class="mi">1</span><span class="p">,</span><span class="w"> </span><span class="ow">in</span><span class="w"> </span><span class="o">&lt;</span><span class="n">module</span><span class="o">&gt;</span>
<span class="w">  </span><span class="n">File</span><span class="w"> </span><span class="s2">&quot;C:\devbisme\KiCad</span><span class="se">\t</span><span class="s2">ools\skidl\skidl\Pin.py&quot;</span><span class="p">,</span><span class="w"> </span><span class="n">line</span><span class="w"> </span><span class="mi">251</span><span class="p">,</span><span class="w"> </span><span class="ow">in</span><span class="w"> </span><span class="n">__getitem__</span>
<span class="w">    </span><span class="n">raise</span><span class="w"> </span><span class="n">Exception</span>
<span class="n">Exception</span>
</code></pre></div>

<p><strong>Iterators:</strong>
  In addition to supporting indexing, <code>Pin</code>, <code>Net</code> and <code>Bus</code> objects can be used
  as iterators.</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="nv">bus</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nv">Bus</span><span class="ss">(</span><span class="s1">&#39;bus&#39;</span>,<span class="w"> </span><span class="mi">4</span><span class="ss">)</span>
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="k">for</span><span class="w"> </span><span class="nv">line</span><span class="w"> </span><span class="nv">in</span><span class="w"> </span><span class="nv">bus</span>:
<span class="w">    </span>...:<span class="w">     </span><span class="nv">print</span><span class="ss">(</span><span class="nv">line</span><span class="ss">)</span>
<span class="w">    </span>...:
<span class="nv">bus0</span>:
<span class="nv">bus1</span>:
<span class="nv">bus2</span>:
<span class="nv">bus3</span>:
</code></pre></div>

<p><strong>Width</strong>:
    <code>Bus</code>, <code>Net</code>, and <code>Pin</code> objects all support the <code>width</code> property.
    For a <code>Bus</code> object, <code>width</code> returns the number of bus lines it contains.
    For a <code>Net</code> or <code>Pin</code> object, <code>width</code> always returns 1.</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; a = Net(&#39;A&#39;)
&gt;&gt;&gt; b = Bus(&#39;B&#39;, 8)
&gt;&gt;&gt; c = Pin()
&gt;&gt;&gt; a.width
1
&gt;&gt;&gt; b.width
8
&gt;&gt;&gt; c.width
1
</code></pre></div>

<h3 id="disambiguating-part-pins-with-identical-names">Disambiguating Part Pins with Identical Names</h3>
<p>If multiple pins of a part are given the same name or alias, then accessing a pin using 
that name will return a list:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span> <span class="n">mcu</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;MCU_ST_STM32F1&#39;</span><span class="p">,</span><span class="s1">&#39;STM32F100C_4-6_Tx&#39;</span><span class="p">)</span>
<span class="o">&gt;&gt;&gt;</span> <span class="n">mcu</span><span class="p">[</span><span class="s2">&quot;SPI1_SCK&quot;</span><span class="p">]</span>
<span class="p">[</span><span class="n">Pin</span> <span class="n">U1</span><span class="o">/</span><span class="mi">39</span><span class="o">/</span><span class="n">PB3</span><span class="p">,</span><span class="n">p39</span><span class="p">,</span><span class="n">TIM2_CH2</span><span class="p">,</span><span class="n">PB3</span><span class="p">,</span><span class="n">SPI1_SCK</span><span class="p">,</span><span class="n">SYS_JTDO</span><span class="o">-</span><span class="n">TRACESWO</span><span class="o">/</span><span class="n">BIDIRECTIONAL</span><span class="p">,</span>
 <span class="n">Pin</span> <span class="n">U1</span><span class="o">/</span><span class="mi">15</span><span class="o">/</span><span class="n">PA5</span><span class="p">,</span><span class="n">DAC_OUT2</span><span class="p">,</span><span class="n">p15</span><span class="p">,</span><span class="n">SPI1_SCK</span><span class="p">,</span><span class="n">ADC1_IN5</span><span class="p">,</span><span class="n">PA5</span><span class="o">/</span><span class="n">BIDIRECTIONAL</span><span class="p">]</span>
</code></pre></div>

<p>To select only one of the pins, use chained indexing as shown here:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span> <span class="n">mcu</span><span class="p">[</span><span class="s2">&quot;SPI1_SCK&quot;</span><span class="p">][</span><span class="s2">&quot;PB3&quot;</span><span class="p">]</span>  <span class="c1"># Use a unique pin name</span>
<span class="n">Pin</span> <span class="n">U1</span><span class="o">/</span><span class="mi">39</span><span class="o">/</span><span class="n">PB3</span><span class="p">,</span><span class="n">p39</span><span class="p">,</span><span class="n">TIM2_CH2</span><span class="p">,</span><span class="n">PB3</span><span class="p">,</span><span class="n">SPI1_SCK</span><span class="p">,</span><span class="n">SYS_JTDO</span><span class="o">-</span><span class="n">TRACESWO</span><span class="o">/</span><span class="n">BIDIRECTIONAL</span>

<span class="o">&gt;&gt;&gt;</span> <span class="n">mcu</span><span class="p">[</span><span class="s2">&quot;SPI1_SCK&quot;</span><span class="p">]</span><span class="o">.</span><span class="n">p39</span>     <span class="c1"># Use a unique pin attribute</span>
<span class="n">Pin</span> <span class="n">U1</span><span class="o">/</span><span class="mi">39</span><span class="o">/</span><span class="n">PB3</span><span class="p">,</span><span class="n">p39</span><span class="p">,</span><span class="n">TIM2_CH2</span><span class="p">,</span><span class="n">PB3</span><span class="p">,</span><span class="n">SPI1_SCK</span><span class="p">,</span><span class="n">SYS_JTDO</span><span class="o">-</span><span class="n">TRACESWO</span><span class="o">/</span><span class="n">BIDIRECTIONAL</span>

<span class="o">&gt;&gt;&gt;</span> <span class="n">mcu</span><span class="p">[</span><span class="s2">&quot;SPI1_SCK&quot;</span><span class="p">][</span><span class="mi">39</span><span class="p">]</span>     <span class="c1"># Use the pin number</span>
<span class="n">Pin</span> <span class="n">U1</span><span class="o">/</span><span class="mi">39</span><span class="o">/</span><span class="n">PB3</span><span class="p">,</span><span class="n">p39</span><span class="p">,</span><span class="n">TIM2_CH2</span><span class="p">,</span><span class="n">PB3</span><span class="p">,</span><span class="n">SPI1_SCK</span><span class="p">,</span><span class="n">SYS_JTDO</span><span class="o">-</span><span class="n">TRACESWO</span><span class="o">/</span><span class="n">BIDIRECTIONAL</span>
</code></pre></div>

<h3 id="part-like-access-of-subcircuit-modules">Part-Like Access of Subcircuit Modules</h3>
<p>Modules created as <a href="#method-2-subcircuit-subclassing-with-io-attributes">subclasses of <code>SubCircuit</code></a> can be
used like parts with named pins as shown below:</p>
<div class="highlight"><pre><span></span><code><span class="k">class</span> <span class="nc">VoltageDivider</span><span class="p">(</span><span class="n">SubCircuit</span><span class="p">):</span>
    <span class="k">def</span> <span class="fm">__init__</span><span class="p">(</span><span class="bp">self</span><span class="p">,</span> <span class="o">*</span><span class="n">args</span><span class="p">,</span> <span class="o">**</span><span class="n">kwargs</span><span class="p">):</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">initialize</span><span class="p">(</span><span class="o">*</span><span class="n">args</span><span class="p">,</span> <span class="o">**</span><span class="n">kwargs</span><span class="p">)</span>

        <span class="c1"># Create local nets</span>
        <span class="n">vin</span><span class="p">,</span> <span class="n">vout</span><span class="p">,</span> <span class="n">gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(),</span> <span class="n">Net</span><span class="p">(),</span> <span class="n">Net</span><span class="p">()</span>

        <span class="c1"># Create resistors</span>
        <span class="n">r1</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="s2">&quot;R&quot;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s2">&quot;10k&quot;</span><span class="p">)</span>
        <span class="n">r2</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="s2">&quot;R&quot;</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s2">&quot;20k&quot;</span><span class="p">)</span>

        <span class="c1"># Create a voltage divider</span>
        <span class="n">vin</span> <span class="o">&amp;</span> <span class="n">r1</span> <span class="o">&amp;</span> <span class="n">vout</span> <span class="o">&amp;</span> <span class="n">r2</span> <span class="o">&amp;</span> <span class="n">gnd</span>

        <span class="c1"># Define I/O pins for the subcircuit module</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">create_pins</span><span class="p">(</span><span class="s2">&quot;VIN&quot;</span><span class="p">,</span> <span class="n">connections</span><span class="o">=</span><span class="n">vin</span><span class="p">)</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">create_pins</span><span class="p">(</span><span class="s2">&quot;VOUT&quot;</span><span class="p">,</span> <span class="n">connections</span><span class="o">=</span><span class="n">vout</span><span class="p">)</span>
        <span class="bp">self</span><span class="o">.</span><span class="n">create_pins</span><span class="p">(</span><span class="s2">&quot;GND&quot;</span><span class="p">,</span> <span class="n">connections</span><span class="o">=</span><span class="n">gnd</span><span class="p">)</span>

        <span class="bp">self</span><span class="o">.</span><span class="n">finalize</span><span class="p">()</span>

<span class="c1"># Instantiate the voltage divider module</span>
<span class="n">vdiv</span> <span class="o">=</span> <span class="n">VoltageDivider</span><span class="p">()</span>

<span class="c1"># Connect the voltage divider module I/O using part-like syntax</span>
<span class="n">vdiv</span><span class="p">[</span><span class="s1">&#39;VIN&#39;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;+5V&#39;</span><span class="p">)</span>   <span class="c1"># Using pin name as index</span>
<span class="n">vdiv</span><span class="o">.</span><span class="n">VOUT</span>   <span class="o">+=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;2.5V&#39;</span><span class="p">)</span>  <span class="c1"># Using pin name as attribute</span>
<span class="n">vdiv</span><span class="p">[</span><span class="mi">3</span><span class="p">]</span>     <span class="o">+=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;GND&#39;</span><span class="p">)</span>   <span class="c1"># Using pin number</span>
</code></pre></div>

<h3 id="selectively-supressing-erc-messages">Selectively Supressing ERC Messages</h3>
<p>Sometimes a portion of your circuit throws a lot of ERC warnings or errors
even though you know it's correct.
SKiDL provides flags that allow you to turn off the ERC for selected nets, pins,
and parts like so:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_net</span><span class="o">.</span><span class="n">do_erc</span> <span class="o">=</span> <span class="kc">False</span>      <span class="c1"># Turns of ERC for this particular net.</span>
<span class="n">my_part</span><span class="p">[</span><span class="mi">5</span><span class="p">]</span><span class="o">.</span><span class="n">do_erc</span> <span class="o">=</span> <span class="kc">False</span>  <span class="c1"># Turns off ERC for this pin of this part.</span>
<span class="n">my_part</span><span class="o">.</span><span class="n">do_erc</span> <span class="o">=</span> <span class="kc">False</span>     <span class="c1"># Turns off ERC for all the pins of this part.</span>
</code></pre></div>

<h3 id="customizable-erc-using-erc_assert">Customizable ERC Using <code>erc_assert()</code></h3>
<p>SKiDL's default ERC will find commonplace design errors, but sometimes
you'll have special requirements.
The <code>erc_assert</code> function is used to check these.</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>
<span class="kn">import</span> <span class="nn">sys</span>

<span class="c1"># Function to check the number of inputs on a net.</span>
<span class="k">def</span> <span class="nf">get_fanout</span><span class="p">(</span><span class="n">net</span><span class="p">):</span>
    <span class="n">fanout</span> <span class="o">=</span> <span class="mi">0</span>
    <span class="k">for</span> <span class="n">pin</span> <span class="ow">in</span> <span class="n">net</span><span class="o">.</span><span class="n">get_pins</span><span class="p">():</span>
        <span class="k">if</span> <span class="n">pin</span><span class="o">.</span><span class="n">func</span> <span class="ow">in</span> <span class="p">(</span><span class="n">Pin</span><span class="o">.</span><span class="n">INPUT</span><span class="p">,</span> <span class="n">Pin</span><span class="o">.</span><span class="n">BIDIR</span><span class="p">):</span>
            <span class="n">fanout</span> <span class="o">+=</span> <span class="mi">1</span>
    <span class="k">return</span> <span class="n">fanout</span>

<span class="n">net1</span><span class="p">,</span> <span class="n">net2</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;IN1&#39;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;IN2&#39;</span><span class="p">)</span>

<span class="c1"># Place some assertions on the fanout of each net.</span>
<span class="c1"># Note that the assertions are passed as strings.</span>
<span class="n">erc_assert</span><span class="p">(</span><span class="s1">&#39;get_fanout(net1) &lt; 5&#39;</span><span class="p">,</span> <span class="s1">&#39;failed on net1&#39;</span><span class="p">)</span>
<span class="n">erc_assert</span><span class="p">(</span><span class="s1">&#39;get_fanout(net2) &lt; 5&#39;</span><span class="p">,</span> <span class="s1">&#39;failed on net2&#39;</span><span class="p">)</span>

<span class="c1"># Attach some pins to the nets.</span>
<span class="n">net1</span> <span class="o">+=</span> <span class="n">Pin</span><span class="p">(</span><span class="n">func</span><span class="o">=</span><span class="n">Pin</span><span class="o">.</span><span class="n">OUTPUT</span><span class="p">)</span>
<span class="n">net2</span> <span class="o">+=</span> <span class="n">Pin</span><span class="p">(</span><span class="n">func</span><span class="o">=</span><span class="n">Pin</span><span class="o">.</span><span class="n">OUTPUT</span><span class="p">)</span>
<span class="n">net1</span> <span class="o">+=</span> <span class="n">Pin</span><span class="p">(</span><span class="n">func</span><span class="o">=</span><span class="n">Pin</span><span class="o">.</span><span class="n">INPUT</span><span class="p">)</span> <span class="o">*</span> <span class="mi">4</span>  <span class="c1"># This net passes the assertion.</span>
<span class="n">net2</span> <span class="o">+=</span> <span class="n">Pin</span><span class="p">(</span><span class="n">func</span><span class="o">=</span><span class="n">Pin</span><span class="o">.</span><span class="n">INPUT</span><span class="p">)</span> <span class="o">*</span> <span class="mi">5</span>  <span class="c1"># This net fails because of too much fanout.</span>

<span class="c1"># When the ERC runs, it will also run any erc_assert statements.</span>
<span class="n">ERC</span><span class="p">()</span>
</code></pre></div>

<p>When you run this code, the ERC will output the following:</p>
<div class="highlight"><pre><span></span><code>ERC ERROR: get_fanout(input_net2) &lt; 5 failed on net2 in &lt;ipython-input-114-5b71f80eb001&gt;:16:&lt;module&gt;.

0 warnings found during ERC.
1 errors found during ERC.
</code></pre></div>

<p>You might ask: "Why not just use the standard Python <code>assert</code> statement?"
The reason is that an <code>assert</code> statement is evaluated as soon as it is encountered
and would give incorrect results if the nets or other circuit objects are not yet
completely defined.
But the statement passed to the <code>erc_assert</code> function isn't evaluated until all the 
various parts have been connected and <code>ERC()</code> is called
(that's why the statement is passed as a string).
Note in the code above that when the <code>erc_assert</code> function is called, no pins
are even attached to the <code>net1</code> or <code>net2</code> nets, yet.
The <code>erc_assert</code> function just places the statements to be checked into a queue
that gets evaluated when <code>ERC()</code> is run.</p>
<h3 id="handling-empty-footprints">Handling Empty Footprints</h3>
<p>When you're creating a new design, it's common to get an error during netlist generation about parts
that are missing footprints.
(Although, parts will try to use the footprint specified in their library definition, if available.)
You can use <a href="#zyc-a-gui-search-tool">zyc</a> to find appropriate footprints one-by-one, but sometimes you just want an
automatic method to assign footprints that are <em>close enough</em>.
This can be done using the <code>empty_footprint_handler</code> function that gets called for any
component found missing its footprint.
For example, the following function assigns an 0805 footprint to any two-pin RLC component lacking
a footprint:</p>
<div class="highlight"><pre><span></span><code><span class="k">def</span> <span class="nf">my_empty_footprint_handler</span><span class="p">(</span><span class="n">part</span><span class="p">):</span>
<span class="w">    </span><span class="sd">&quot;&quot;&quot;Function for handling parts with no footprint.</span>

<span class="sd">    Args:</span>
<span class="sd">        part (Part): Part with no footprint.</span>
<span class="sd">    &quot;&quot;&quot;</span>
    <span class="n">ref_prefix</span> <span class="o">=</span> <span class="n">part</span><span class="o">.</span><span class="n">ref_prefix</span><span class="o">.</span><span class="n">upper</span><span class="p">()</span>

    <span class="k">if</span> <span class="n">ref_prefix</span> <span class="ow">in</span> <span class="p">(</span><span class="s2">&quot;R&quot;</span><span class="p">,</span> <span class="s2">&quot;C&quot;</span><span class="p">,</span> <span class="s2">&quot;L&quot;</span><span class="p">)</span> <span class="ow">and</span> <span class="nb">len</span><span class="p">(</span><span class="n">part</span><span class="o">.</span><span class="n">pins</span><span class="p">)</span> <span class="o">==</span> <span class="mi">2</span><span class="p">:</span>
        <span class="c1"># Resistors, capacitors, inductors default to 0805 SMD footprint.</span>
        <span class="n">part</span><span class="o">.</span><span class="n">footprint</span> <span class="o">=</span> <span class="s2">&quot;Resistor_SMD:R_0805_2012Metric&quot;</span>

    <span class="k">else</span><span class="p">:</span>
        <span class="c1"># Everything else just gets this ridiculous footprint to avoid raising exceptions.</span>
        <span class="n">part</span><span class="o">.</span><span class="n">footprint</span> <span class="o">=</span> <span class="s2">&quot;:&quot;</span>
</code></pre></div>

<p>Then, install the custom footprint handler anywhere before the <code>generate_netlist</code> function is called,
like so:</p>
<div class="highlight"><pre><span></span><code><span class="c1"># Install the footprint handler for these tests.</span>
<span class="kn">import</span> <span class="nn">skidl</span>
<span class="n">skidl</span><span class="o">.</span><span class="n">empty_footprint_handler</span> <span class="o">=</span> <span class="n">my_empty_footprint_handler</span>
</code></pre></div>

<h3 id="tags">Tags</h3>
<p>If you don't assign part references (e.g., <code>R1</code>), SKiDL will do it automatically.
This saves effort on your part, but if you insert a new part into an existing design,
all the part references probably will change during the automatic renumbering.
If you already have a PCB layout that associates the footprints to the parts in the netlist
using the old references, then the PCB wiring may no longer be consistent with the netlist.</p>
<p>To avoid this problem, <em>tags</em>
can be assigned to parts and subcircuits:</p>
<div class="highlight"><pre><span></span><code><span class="nd">@subcircuit</span>
<span class="k">def</span> <span class="nf">vdiv</span><span class="p">(</span><span class="n">inp</span><span class="p">,</span> <span class="n">outp</span><span class="p">):</span>
<span class="w">    </span><span class="sd">&quot;&quot;&quot;Divide inp voltage by 3 and place it on outp net.&quot;&quot;&quot;</span>
    <span class="c1"># Assign a different tag to each resistor.</span>
    <span class="n">inp</span> <span class="o">&amp;</span> <span class="n">r</span><span class="p">(</span><span class="n">value</span><span class="o">=</span><span class="s1">&#39;1K&#39;</span><span class="p">,</span> <span class="n">tag</span><span class="o">=</span><span class="s1">&#39;r_upper&#39;</span><span class="p">)</span> <span class="o">&amp;</span> <span class="n">outp</span> <span class="o">&amp;</span> <span class="n">r</span><span class="p">(</span><span class="n">value</span><span class="o">=</span><span class="s1">&#39;500&#39;</span><span class="p">,</span> <span class="n">tag</span><span class="o">=</span><span class="s1">&#39;r_lower&#39;</span><span class="p">)</span> <span class="o">&amp;</span> <span class="n">gnd</span>

<span class="n">vdiv</span><span class="p">(</span><span class="n">in1</span><span class="p">,</span> <span class="n">out1</span><span class="p">,</span> <span class="n">tag</span><span class="o">=</span><span class="s1">&#39;vdiv1&#39;</span><span class="p">)</span>  <span class="c1"># Create voltage divider with tag &#39;vdiv1&#39;.</span>
<span class="n">vdiv</span><span class="p">(</span><span class="n">in2</span><span class="p">,</span> <span class="n">out2</span><span class="p">,</span> <span class="n">tag</span><span class="o">=</span><span class="s1">&#39;vdiv2&#39;</span><span class="p">)</span>  <span class="c1"># Create another with tag &#39;vdiv2&#39;.</span>
</code></pre></div>

<p>Using tags (which can be any printable object such as a string or number), the
<em>timestamps</em> for the resistors in the two voltage dividers will be the same no matter 
the order in which the subcircuits or the internal resistors are instantiated even though
the automatically-assigned references of the resistors will change.
The resulting netlist can be imported into layout editors like KiCad's PCBNEW using the
timestamps (instead of part references) and will remain consistent with the PCB
wiring traces.</p>
<h3 id="configuration-file">Configuration File</h3>
<p>SKiDL's configuration file lets you override the default settings.
You can store the current settings by running the following command:</p>
<div class="highlight"><pre><span></span><code><span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="kn">from</span><span class="w"> </span><span class="nn">skidl</span><span class="w"> </span><span class="kn">import</span><span class="w"> </span><span class="o">*</span>
<span class="o">&gt;&gt;&gt;</span><span class="w"> </span><span class="n">skidl</span><span class="o">.</span><span class="n">config</span><span class="o">.</span><span class="n">store</span><span class="p">(</span><span class="s1">&#39;.&#39;</span><span class="p">)</span>
</code></pre></div>

<p>The <code>.skidlcfg</code> JSON file with the SKiDL settings will be created in the current directory:</p>
<div class="highlight"><pre><span></span><code><span class="p">{</span>
<span class="w">    </span><span class="nt">&quot;cfg_file_name&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;.skidlcfg&quot;</span><span class="p">,</span>
<span class="w">    </span><span class="nt">&quot;tool&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;kicad9&quot;</span><span class="p">,</span>
<span class="w">    </span><span class="nt">&quot;pickle_dir&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;./lib_pickle_dir&quot;</span><span class="p">,</span>
<span class="w">    </span><span class="nt">&quot;lib_search_paths&quot;</span><span class="p">:</span><span class="w"> </span><span class="p">{</span>
<span class="w">        </span><span class="nt">&quot;kicad8&quot;</span><span class="p">:</span><span class="w"> </span><span class="p">[</span>
<span class="w">            </span><span class="s2">&quot;.&quot;</span><span class="p">,</span>
<span class="w">            </span><span class="s2">&quot;/usr/share/kicad/symbols&quot;</span>
<span class="w">        </span><span class="p">],</span>
<span class="w">        </span><span class="nt">&quot;spice&quot;</span><span class="p">:</span><span class="w"> </span><span class="p">[</span>
<span class="w">            </span><span class="s2">&quot;.&quot;</span>
<span class="w">        </span><span class="p">],</span>
<span class="w">        </span><span class="nt">&quot;kicad7&quot;</span><span class="p">:</span><span class="w"> </span><span class="p">[</span>
<span class="w">            </span><span class="s2">&quot;.&quot;</span><span class="p">,</span>
<span class="w">            </span><span class="s2">&quot;/usr/share/kicad/symbols&quot;</span>
<span class="w">        </span><span class="p">],</span>
<span class="w">        </span><span class="nt">&quot;kicad6&quot;</span><span class="p">:</span><span class="w"> </span><span class="p">[</span>
<span class="w">            </span><span class="s2">&quot;.&quot;</span><span class="p">,</span>
<span class="w">            </span><span class="s2">&quot;/usr/share/kicad/symbols&quot;</span>
<span class="w">        </span><span class="p">],</span>
<span class="w">        </span><span class="nt">&quot;kicad9&quot;</span><span class="p">:</span><span class="w"> </span><span class="p">[</span>
<span class="w">            </span><span class="s2">&quot;.&quot;</span><span class="p">,</span>
<span class="w">            </span><span class="s2">&quot;/usr/share/kicad/symbols&quot;</span>
<span class="w">        </span><span class="p">],</span>
<span class="w">        </span><span class="nt">&quot;skidl&quot;</span><span class="p">:</span><span class="w"> </span><span class="p">[</span>
<span class="w">            </span><span class="s2">&quot;.&quot;</span><span class="p">,</span>
<span class="w">            </span><span class="s2">&quot;/home/devb/projects/KiCad/tools/skidl/src/skidl/tools/skidl/libs&quot;</span>
<span class="w">        </span><span class="p">],</span>
<span class="w">        </span><span class="nt">&quot;kicad5&quot;</span><span class="p">:</span><span class="w"> </span><span class="p">[</span>
<span class="w">            </span><span class="s2">&quot;.&quot;</span><span class="p">,</span>
<span class="w">            </span><span class="s2">&quot;/usr/share/kicad/library&quot;</span>
<span class="w">        </span><span class="p">]</span>
<span class="w">    </span><span class="p">},</span>
<span class="w">    </span><span class="nt">&quot;backup_lib_name&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;skidl_REPL&quot;</span><span class="p">,</span>
<span class="w">    </span><span class="nt">&quot;backup_lib_file_name&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;skidl_REPL_sklib.py&quot;</span><span class="p">,</span>
<span class="w">    </span><span class="nt">&quot;query_backup_lib&quot;</span><span class="p">:</span><span class="w"> </span><span class="kc">true</span><span class="p">,</span>
<span class="w">    </span><span class="nt">&quot;backup_lib&quot;</span><span class="p">:</span><span class="w"> </span><span class="kc">null</span><span class="p">,</span>
<span class="w">    </span><span class="nt">&quot;footprint_search_paths&quot;</span><span class="p">:</span><span class="w"> </span><span class="p">{</span>
<span class="w">        </span><span class="nt">&quot;kicad8&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;/home/devb/.config/kicad/8.0&quot;</span><span class="p">,</span>
<span class="w">        </span><span class="nt">&quot;spice&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;&quot;</span><span class="p">,</span>
<span class="w">        </span><span class="nt">&quot;kicad7&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;/home/devb/.config/kicad/7.0&quot;</span><span class="p">,</span>
<span class="w">        </span><span class="nt">&quot;kicad6&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;/home/devb/.config/kicad/6.0&quot;</span><span class="p">,</span>
<span class="w">        </span><span class="nt">&quot;kicad9&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;/home/devb/.config/kicad/9.0&quot;</span><span class="p">,</span>
<span class="w">        </span><span class="nt">&quot;skidl&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;&quot;</span><span class="p">,</span>
<span class="w">        </span><span class="nt">&quot;kicad5&quot;</span><span class="p">:</span><span class="w"> </span><span class="s2">&quot;/home/devb/.config/kicad&quot;</span>
<span class="w">    </span><span class="p">}</span>
<span class="p">}</span>
</code></pre></div>

<p>You can modify any of the settings in this file to reflect your preferences.
Then store it in your home directory to use it as the default configuration
for all your SKiDL projects.
Or store it in a directory where you're working on a specific project to
have it only apply to that project.</p>
<h1 id="going-really-deep">Going Really Deep</h1>
<p>If all you need to do is design the circuitry for a PCB, then you probably know
all the SKiDL you need to know.
This section will describe the features of SKiDL that might be useful (or not) to
some of the avant-garde circuit designers out there.</p>
<h2 id="ad-hoc-parts">Ad-Hoc Parts</h2>
<p>While you'll most often use parts found in libraries,
you can also create ad-hoc parts on the fly:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_part</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="n">name</span><span class="o">=</span><span class="s1">&#39;R&#39;</span><span class="p">,</span> <span class="n">tool</span><span class="o">=</span><span class="n">SKIDL</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)</span> <span class="c1"># Create an empty part object template.</span>
<span class="n">my_part</span><span class="o">.</span><span class="n">ref_prefix</span> <span class="o">=</span> <span class="s1">&#39;R&#39;</span>                            <span class="c1"># Set the part&#39;s reference prefix.</span>
<span class="n">my_part</span><span class="o">.</span><span class="n">description</span> <span class="o">=</span> <span class="s1">&#39;resistor&#39;</span>                    <span class="c1"># Set the part&#39;s description field.</span>
<span class="n">my_part</span><span class="o">.</span><span class="n">keywords</span> <span class="o">=</span> <span class="s1">&#39;res resistor&#39;</span>                   <span class="c1"># Set the part&#39;s keywords.</span>
<span class="n">my_part</span> <span class="o">+=</span> <span class="n">Pin</span><span class="p">(</span><span class="n">num</span><span class="o">=</span><span class="mi">1</span><span class="p">,</span> <span class="n">func</span><span class="o">=</span><span class="n">Pin</span><span class="o">.</span><span class="n">funcs</span><span class="o">.</span><span class="n">PASSIVE</span><span class="p">)</span>       <span class="c1"># Add a pin to the part.</span>
<span class="n">my_part</span> <span class="o">+=</span> <span class="n">Pin</span><span class="p">(</span><span class="n">num</span><span class="o">=</span><span class="mi">2</span><span class="p">,</span> <span class="n">func</span><span class="o">=</span><span class="n">Pin</span><span class="o">.</span><span class="n">funcs</span><span class="o">.</span><span class="n">PASSIVE</span><span class="p">)</span>       <span class="c1"># Add another pin to the part.</span>
<span class="n">new_resistor</span> <span class="o">=</span> <span class="n">my_part</span><span class="p">()</span>                            <span class="c1"># Instantiate the part from the template.</span>
</code></pre></div>

<p>Always create an ad-hoc part as a template so it isn't inadvertently
added to the circuit netlist.
Then set the part attributes and create and add pins to the part.
Here are the most common attributes you'll want to set:</p>
<table>
<thead>
<tr>
<th>Attribute</th>
<th>Meaning</th>
</tr>
</thead>
<tbody>
<tr>
<td>name</td>
<td>A string containing the name of the part, e.g. 'LM35' for a temperature sensor.</td>
</tr>
<tr>
<td>ref_prefix</td>
<td>A string containing the prefix for this part's references, e.g. 'U' for ICs.</td>
</tr>
<tr>
<td>description</td>
<td>A string describing the part, e.g. 'temperature sensor'.</td>
</tr>
<tr>
<td>keywords</td>
<td>A string containing keywords about the part, e.g. 'sensor temperature IC'.</td>
</tr>
<tr>
<td>footprint</td>
<td>A string containing the footprint of the part, e.g. 'Resistor_SMD.pretty:R_0805_2012Metric'.</td>
</tr>
</tbody>
</table>
<p>When creating pins, these are the attributes you'll want to set:</p>
<table>
<thead>
<tr>
<th>Attribute</th>
<th>Meaning</th>
</tr>
</thead>
<tbody>
<tr>
<td>num</td>
<td>A string or integer containing the pin number, e.g. 5 or 'A13'.</td>
</tr>
<tr>
<td>name</td>
<td>A string containing the name of the pin, e.g. 'CS'.</td>
</tr>
<tr>
<td>func</td>
<td>An identifier for the function of the pin.</td>
</tr>
</tbody>
</table>
<p>The pin function identifiers are as follows:</p>
<table>
<thead>
<tr>
<th>Identifier</th>
<th>Pin Function</th>
</tr>
</thead>
<tbody>
<tr>
<td>Pin.funcs.INPUT</td>
<td>Input pin.</td>
</tr>
<tr>
<td>Pin.funcs.OUTPUT</td>
<td>Output pin.</td>
</tr>
<tr>
<td>Pin.funcs.BIDIR</td>
<td>Bidirectional in/out pin.</td>
</tr>
<tr>
<td>Pin.funcs.TRISTATE</td>
<td>Output pin that goes into a high-impedance state when disabled.</td>
</tr>
<tr>
<td>Pin.funcs.PASSIVE</td>
<td>Pin on a passive component (like a resistor).</td>
</tr>
<tr>
<td>Pin.funcs.UNSPEC</td>
<td>Pin with an unspecified function.</td>
</tr>
<tr>
<td>Pin.funcs.PWRIN</td>
<td>Power input pin (either voltage supply or ground).</td>
</tr>
<tr>
<td>Pin.funcs.PWROUT</td>
<td>Power output pin (like the output of a voltage regulator).</td>
</tr>
<tr>
<td>Pin.funcs.OPENCOLL</td>
<td>Open-collector pin (pulls to ground but not to positive rail).</td>
</tr>
<tr>
<td>Pin.funcs.OPENEMIT</td>
<td>Open-emitter pin (pulls to positive rail but not to ground).</td>
</tr>
<tr>
<td>Pin.funcs.PULLUP</td>
<td>Pin with a pull-up resistor.</td>
</tr>
<tr>
<td>Pin.funcs.PULLDOWN</td>
<td>Pin with a pull-down resistor.</td>
</tr>
<tr>
<td>Pin.funcs.NOCONNECT</td>
<td>A pin that should be left unconnected.</td>
</tr>
<tr>
<td>Pin.funcs.FREE</td>
<td>A pin that is free to be used for any function.</td>
</tr>
</tbody>
</table>
<h2 id="circuit-objects">Circuit Objects</h2>
<p>Normally, SKiDL puts parts and nets into a global instance of a <code>Circuit</code> object
called <code>default_circuit</code> (which, of course, you never noticed).
But you can create other <code>Circuit</code> objects:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; my_circuit = Circuit()
</code></pre></div>

<p>and then you can create parts, nets and buses and add them to your new circuit:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; my_circuit += Part(&quot;Device&quot;,&#39;R&#39;)  # Add a resistor to the circuit.
&gt;&gt;&gt; my_circuit += Net(&#39;GND&#39;)          # Add a net.
&gt;&gt;&gt; my_circuit += Bus(&#39;byte_bus&#39;, 8)  # Add a bus.
</code></pre></div>

<p>In addition to the <code>+=</code> operator, you can also use the methods <code>add_parts</code>, <code>add_nets</code>, and <code>add_buses</code>.
(There's also the much less-used <code>-=</code> operator for removing parts, nets or buses
from a circuit along with the <code>rmv_parts</code>, <code>rmv_nets</code>, and <code>rmv_buses</code> methods.)</p>
<p>Parts, nets, and buses can also be added directly to a <code>Circuit</code> object
by using the <code>circuit</code> parameter of the object constructors:</p>
<div class="highlight"><pre><span></span><code>&gt;&gt;&gt; my_circuit = Circuit()
&gt;&gt;&gt; p = Part(&quot;Device&quot;, &#39;R&#39;, circuit = my_circuit)
&gt;&gt;&gt; n = Net(&#39;GND&#39;, circuit = my_circuit)
&gt;&gt;&gt; b = Bus(&#39;byte_bus&#39;, 8, circuit = my_circuit)
</code></pre></div>

<p>Alternatively, you can use a context manager inside which a <code>Circuit</code> object
becomes the <code>default_circuit</code>:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_circuit</span> <span class="o">=</span> <span class="n">Circuit</span><span class="p">()</span>
<span class="k">with</span> <span class="n">my_circuit</span><span class="p">:</span>
    <span class="n">p</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">&#39;Device&#39;</span><span class="p">,</span> <span class="s1">&#39;R&#39;</span><span class="p">)</span>
    <span class="n">n</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;GND&#39;</span><span class="p">)</span>
    <span class="n">b</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">&#39;byte_bus&#39;</span><span class="p">,</span> <span class="mi">8</span><span class="p">)</span>
</code></pre></div>

<p>Hierarchical circuits such as this cascaded voltage divider also work with <code>Circuit</code> objects:</p>
<div class="highlight"><pre><span></span><code><span class="nd">@subcircuit</span>
<span class="k">def</span> <span class="nf">vdiv</span><span class="p">(</span><span class="n">inp</span><span class="p">,</span> <span class="n">outp</span><span class="p">):</span>
    <span class="n">r</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="s2">&quot;R&quot;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)</span>
    <span class="n">inp</span> <span class="o">&amp;</span> <span class="n">r</span><span class="p">(</span><span class="n">value</span><span class="o">=</span><span class="s1">&#39;1K&#39;</span><span class="p">,</span> <span class="n">tag</span><span class="o">=</span><span class="s1">&#39;r_upper&#39;</span><span class="p">)</span> <span class="o">&amp;</span> <span class="n">outp</span> <span class="o">&amp;</span> <span class="n">r</span><span class="p">(</span><span class="n">value</span><span class="o">=</span><span class="s1">&#39;500&#39;</span><span class="p">,</span> <span class="n">tag</span><span class="o">=</span><span class="s1">&#39;r_lower&#39;</span><span class="p">)</span> <span class="o">&amp;</span> <span class="n">gnd</span>

<span class="nd">@subcircuit</span>
<span class="k">def</span> <span class="nf">casc_vdiv</span><span class="p">(</span><span class="n">inp</span><span class="p">,</span> <span class="n">outp</span><span class="p">):</span>
    <span class="n">outp_middle</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>
    <span class="n">vdiv</span><span class="p">(</span><span class="n">inp</span><span class="p">,</span> <span class="n">outp_middle</span><span class="p">)</span>
    <span class="n">vdiv</span><span class="p">(</span><span class="n">outp_middle</span><span class="p">,</span> <span class="n">outp</span><span class="p">)</span>

<span class="n">my_circuit</span> <span class="o">=</span> <span class="n">Circuit</span><span class="p">()</span>   <span class="c1"># New Circuit object.</span>

<span class="n">gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;GND&#39;</span><span class="p">)</span>         <span class="c1"># GLobal ground net.</span>
<span class="n">input_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;IN&#39;</span><span class="p">)</span>    <span class="c1"># Net with the voltage to be divided.</span>
<span class="n">output_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;OUT&#39;</span><span class="p">)</span>  <span class="c1"># Net with the divided voltage.</span>
<span class="n">my_circuit</span> <span class="o">+=</span> <span class="n">gnd</span><span class="p">,</span> <span class="n">input_net</span><span class="p">,</span> <span class="n">output_net</span>  <span class="c1"># Move the nets to the new circuit.</span>

<span class="c1"># Instantiate the multi-level hierarchical subcircuit into the new Circuit object.</span>
<span class="n">casc_vdiv</span><span class="p">(</span><span class="n">input_net</span><span class="p">,</span> <span class="n">output_net</span><span class="p">,</span> <span class="n">circuit</span> <span class="o">=</span> <span class="n">my_circuit</span><span class="p">)</span>
</code></pre></div>

<p>The actual <code>circuit</code> parameter is not passed on to the subcircuit.
It's extracted and any elements created in the subcircuit are sent there instead of
to the <code>default_circuit</code>.</p>
<p>Hierarchy is also supported when using a context manager:</p>
<div class="highlight"><pre><span></span><code><span class="nd">@subcircuit</span>
<span class="k">def</span> <span class="nf">vdiv</span><span class="p">(</span><span class="n">inp</span><span class="p">,</span> <span class="n">outp</span><span class="p">):</span>
    <span class="n">r</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="s2">&quot;R&quot;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)</span>
    <span class="n">inp</span> <span class="o">&amp;</span> <span class="n">r</span><span class="p">(</span><span class="n">value</span><span class="o">=</span><span class="s1">&#39;1K&#39;</span><span class="p">,</span> <span class="n">tag</span><span class="o">=</span><span class="s1">&#39;r_upper&#39;</span><span class="p">)</span> <span class="o">&amp;</span> <span class="n">outp</span> <span class="o">&amp;</span> <span class="n">r</span><span class="p">(</span><span class="n">value</span><span class="o">=</span><span class="s1">&#39;500&#39;</span><span class="p">,</span> <span class="n">tag</span><span class="o">=</span><span class="s1">&#39;r_lower&#39;</span><span class="p">)</span> <span class="o">&amp;</span> <span class="n">gnd</span>

<span class="nd">@subcircuit</span>
<span class="k">def</span> <span class="nf">casc_vdiv</span><span class="p">(</span><span class="n">inp</span><span class="p">,</span> <span class="n">outp</span><span class="p">):</span>
    <span class="n">outp_middle</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>
    <span class="n">vdiv</span><span class="p">(</span><span class="n">inp</span><span class="p">,</span> <span class="n">outp_middle</span><span class="p">)</span>
    <span class="n">vdiv</span><span class="p">(</span><span class="n">outp_middle</span><span class="p">,</span> <span class="n">outp</span><span class="p">)</span>

<span class="n">my_circuit</span> <span class="o">=</span> <span class="n">Circuit</span><span class="p">()</span>

<span class="k">with</span> <span class="n">my_circuit</span><span class="p">:</span>
    <span class="c1"># Everything instantiated in this context goes into my_circuit.</span>
    <span class="n">gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;GND&#39;</span><span class="p">)</span>
    <span class="n">input_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;IN&#39;</span><span class="p">)</span>
    <span class="n">output_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">&#39;OUT&#39;</span><span class="p">)</span>
    <span class="n">casc_vdiv</span><span class="p">(</span><span class="n">input_net</span><span class="p">,</span> <span class="n">output_net</span><span class="p">)</span>
</code></pre></div>

<p>You may do all the same operations on a <code>Circuit</code> object that are supported on the 
default circuit, such as:</p>
<div class="highlight"><pre><span></span><code><span class="c1"># Check the circuit for errors.</span>
<span class="n">my_circuit</span><span class="o">.</span><span class="n">ERC</span><span class="p">()</span>

<span class="c1"># Generate the netlist from the new Circuit object.</span>
<span class="n">my_circuit</span><span class="o">.</span><span class="n">generate_netlist</span><span class="p">(</span><span class="n">sys</span><span class="o">.</span><span class="n">stdout</span><span class="p">)</span>
</code></pre></div>

<p>Naturally, the presence of multiple, independent circuits creates the possibility of 
new types of errors.
Here are a few things you can't do (and will get warned about):</p>
<ul>
<li>
<p>You can't make connections between parts, nets or buses that reside in 
  different <code>Circuit</code> objects.</p>
</li>
<li>
<p>Once a part, net, or bus is connected to something else in a <code>Circuit</code> object,
  it can't be moved to a different <code>Circuit</code> object.</p>
</li>
</ul>
<h2 id="nodes">Nodes</h2>
<p><code>Node</code> objects are used to store the hierarchy of a circuit.
The top-most node is stored in <code>default_circuit.root</code>.
Every subcircuit has a node associated with it
that can be accessed from <code>default_circuit.active_node</code>
while the code in the subcircuit is being executed.</p>
<p>Some attributes of the <code>Node</code> class are:</p>
<ul>
<li><code>name</code>: The name of the node.</li>
<li><code>parent</code>: The parent node, if any.</li>
<li><code>children</code>: A list of child nodes, if any.</li>
<li><code>parts</code>: A list of parts instantiated within the node.</li>
<li><code>nets</code>: A list of nets instantiated within the node.</li>
<li><code>buses</code>: A list of buses instantiated within the node.</li>
<li><code>partclasses</code>: A list of part classes applied to parts within the node and its children.</li>
<li><code>netclasses</code>: A list of net classes applied to nets within the node and its children.</li>
</ul>
<h1 id="generating-a-schematic">Generating a Schematic</h1>
<p>Although SKiDL lets you avoid the tedious drawing of a schematic, some
still want to see a graphical depiction of their circuit.
To support this, SKiDL can show the interconnection of parts as:</p>
<ul>
<li>a <a href="#svg-schematics">static schematic in SVG</a>,</li>
<li>an <a href="#kicad-schematics">editable KiCad schematic</a> (currently only V5 is supported),</li>
<li>or a <a href="#dot-graphs">directed graph</a> using the <a href="https://graphviz.org/doc/info/lang.html">graphviz DOT language</a>.</li>
</ul>
<p>The following circuit for a transistor-based AND gate will be used to illustrate each alternative:</p>
<p><img alt="TTL AND Gate" src="https://raw.githubusercontent.com/nturley/netlistsvg/master/doc/and.svg?sanitize=true"></p>
<p>The <code>and_gate.py</code> SKiDL script for this circuit is:</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>

<span class="c1"># Create part templates.</span>
<span class="n">q</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="n">lib</span><span class="o">=</span><span class="s2">&quot;Transistor_BJT&quot;</span><span class="p">,</span> <span class="n">name</span><span class="o">=</span><span class="s2">&quot;Q_PNP_CBE&quot;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">,</span> <span class="n">symtx</span><span class="o">=</span><span class="s2">&quot;V&quot;</span><span class="p">)</span>
<span class="n">r</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;Device&quot;</span><span class="p">,</span> <span class="s2">&quot;R&quot;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)</span>

<span class="c1"># Create nets.</span>
<span class="n">gnd</span><span class="p">,</span> <span class="n">vcc</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s2">&quot;GND&quot;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s2">&quot;VCC&quot;</span><span class="p">)</span>
<span class="n">a</span><span class="p">,</span> <span class="n">b</span><span class="p">,</span> <span class="n">a_and_b</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s2">&quot;A&quot;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s2">&quot;B&quot;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s2">&quot;A_AND_B&quot;</span><span class="p">)</span>

<span class="c1"># Instantiate parts.</span>
<span class="n">gndt</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;power&quot;</span><span class="p">,</span> <span class="s2">&quot;GND&quot;</span><span class="p">)</span>  <span class="c1"># Ground terminal.</span>
<span class="n">vcct</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">&quot;power&quot;</span><span class="p">,</span> <span class="s2">&quot;VCC&quot;</span><span class="p">)</span>  <span class="c1"># Power terminal.</span>
<span class="n">q1</span><span class="p">,</span> <span class="n">q2</span> <span class="o">=</span> <span class="n">q</span><span class="p">(</span><span class="mi">2</span><span class="p">)</span>
<span class="n">r1</span><span class="p">,</span> <span class="n">r2</span><span class="p">,</span> <span class="n">r3</span><span class="p">,</span> <span class="n">r4</span><span class="p">,</span> <span class="n">r5</span> <span class="o">=</span> <span class="n">r</span><span class="p">(</span><span class="mi">5</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s2">&quot;10K&quot;</span><span class="p">)</span>

<span class="c1"># Make connections between parts.</span>
<span class="n">a</span> <span class="o">&amp;</span> <span class="n">r1</span> <span class="o">&amp;</span> <span class="n">q1</span><span class="p">[</span><span class="s2">&quot;B&quot;</span><span class="p">,</span> <span class="s2">&quot;C&quot;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">r4</span> <span class="o">&amp;</span> <span class="n">q2</span><span class="p">[</span><span class="s2">&quot;B&quot;</span><span class="p">,</span> <span class="s2">&quot;C&quot;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">a_and_b</span> <span class="o">&amp;</span> <span class="n">r5</span> <span class="o">&amp;</span> <span class="n">gnd</span>
<span class="n">b</span> <span class="o">&amp;</span> <span class="n">r2</span> <span class="o">&amp;</span> <span class="n">q1</span><span class="p">[</span><span class="s2">&quot;B&quot;</span><span class="p">]</span>
<span class="n">q1</span><span class="p">[</span><span class="s2">&quot;C&quot;</span><span class="p">]</span> <span class="o">&amp;</span> <span class="n">r3</span> <span class="o">&amp;</span> <span class="n">gnd</span>
<span class="n">vcc</span> <span class="o">+=</span> <span class="n">q1</span><span class="p">[</span><span class="s2">&quot;E&quot;</span><span class="p">],</span> <span class="n">q2</span><span class="p">[</span><span class="s2">&quot;E&quot;</span><span class="p">],</span> <span class="n">vcct</span>
<span class="n">gnd</span> <span class="o">+=</span> <span class="n">gndt</span>
</code></pre></div>

<h2 id="svg-schematics">SVG Schematics</h2>
<p><strong>Note: Generating SVG schematics requires that you install
<a href="https://github.com/nturley/netlistsvg">netlistsvg</a> on your system:</strong></p>
<div class="highlight"><pre><span></span><code>npm<span class="w"> </span>install<span class="w"> </span>https://github.com/nturley/netlistsvg
</code></pre></div>

<p>You can create a schematic as an SVG file by appending the
following to the end of the script:</p>
<div class="highlight"><pre><span></span><code><span class="n">generate_svg</span><span class="p">()</span>
</code></pre></div>

<p>The resulting <code>and_gate.svg</code> file looks like this:</p>
<p><img alt="AND_GATE schematic." src="images/and_gate_1.svg"></p>
<p>The schematic symbols from the KiCad libraries are converted to create the
SVG, but it still lacks some elements like the input and output terminals.
To add these, modify the script as follows:</p>
<div class="highlight"><pre><span></span><code><span class="n">a</span><span class="o">.</span><span class="n">netio</span> <span class="o">=</span> <span class="s2">&quot;i&quot;</span>        <span class="c1"># Input terminal.</span>
<span class="n">b</span><span class="o">.</span><span class="n">netio</span> <span class="o">=</span> <span class="s2">&quot;i&quot;</span>        <span class="c1"># Input terminal.</span>
<span class="n">a_and_b</span><span class="o">.</span><span class="n">netio</span> <span class="o">=</span> <span class="s2">&quot;o&quot;</span>  <span class="c1"># Output terminal.</span>

<span class="n">generate_svg</span><span class="p">()</span>
</code></pre></div>

<p>Now the schematic looks a little better:</p>
<p><img alt="AND_GATE schematic with terminals." src="images/and_gate_2.svg"></p>
<p>Further improvements are possible by adding some indicators about the "flow"
of the signals through the components:</p>
<div class="highlight"><pre><span></span><code><span class="n">a</span><span class="o">.</span><span class="n">netio</span> <span class="o">=</span> <span class="s2">&quot;i&quot;</span>        <span class="c1"># Input terminal.</span>
<span class="n">b</span><span class="o">.</span><span class="n">netio</span> <span class="o">=</span> <span class="s2">&quot;i&quot;</span>        <span class="c1"># Input terminal.</span>
<span class="n">a_and_b</span><span class="o">.</span><span class="n">netio</span> <span class="o">=</span> <span class="s2">&quot;o&quot;</span>  <span class="c1"># Output terminal.</span>

<span class="n">q1</span><span class="o">.</span><span class="n">E</span><span class="o">.</span><span class="n">symio</span> <span class="o">=</span> <span class="s2">&quot;i&quot;</span>  <span class="c1"># Signal enters Q1 on E and B terminals.</span>
<span class="n">q1</span><span class="o">.</span><span class="n">B</span><span class="o">.</span><span class="n">symio</span> <span class="o">=</span> <span class="s2">&quot;i&quot;</span>
<span class="n">q1</span><span class="o">.</span><span class="n">C</span><span class="o">.</span><span class="n">symio</span> <span class="o">=</span> <span class="s2">&quot;o&quot;</span>  <span class="c1"># Signal exits Q1 on C terminal.</span>
<span class="n">q2</span><span class="o">.</span><span class="n">E</span><span class="o">.</span><span class="n">symio</span> <span class="o">=</span> <span class="s2">&quot;i&quot;</span>  <span class="c1"># Signal enters Q2 on E and B terminals.</span>
<span class="n">q2</span><span class="o">.</span><span class="n">B</span><span class="o">.</span><span class="n">symio</span> <span class="o">=</span> <span class="s2">&quot;i&quot;</span>
<span class="n">q2</span><span class="o">.</span><span class="n">C</span><span class="o">.</span><span class="n">symio</span> <span class="o">=</span> <span class="s2">&quot;o&quot;</span>  <span class="c1"># Signal exits Q2 on C terminal.</span>

<span class="n">generate_svg</span><span class="p">()</span>
</code></pre></div>

<p>Now the schematic looks closer to the original:</p>
<p><img alt="AND_GATE schematic with flow." src="images/and_gate_3.svg"></p>
<p>In addition to the <code>netio</code> and <code>symio</code> attributes, you can also change the
orientation of a part using the <code>symtx</code> attribute.
A string assigned to <code>symtx</code> is processed from left to right with each character
specifying one of the following operations upon the symbol:</p>
<table>
<thead>
<tr>
<th>symtx</th>
<th>Operation</th>
</tr>
</thead>
<tbody>
<tr>
<td>H</td>
<td>Flip symbol horizontally (left to right).</td>
</tr>
<tr>
<td>V</td>
<td>Flip symbol vertically (top to bottom).</td>
</tr>
<tr>
<td>R</td>
<td>Rotate symbol 90$\degree$ to the left (counter clockwise).</td>
</tr>
<tr>
<td>L</td>
<td>Rotate symbol 90$\degree$ to the right (clockwise).</td>
</tr>
</tbody>
</table>
<p>To illustrate, the following would flip transistor <code>q1</code> horizontally
and then rotate it 90$\degree$ clockwise:</p>
<div class="highlight"><pre><span></span><code><span class="n">q1</span><span class="o">.</span><span class="n">symtx</span> <span class="o">=</span> <span class="s2">&quot;HR&quot;</span>  <span class="c1"># Flip horizontally and then rotate right by 90 degrees.</span>
</code></pre></div>

<p>You can also set a net or bus attribute to choose whether it is fully drawn or replaced by
a named <em>stub</em> at each connection point:</p>
<div class="highlight"><pre><span></span><code><span class="n">vcc</span><span class="o">.</span><span class="n">stub</span> <span class="o">=</span> <span class="kc">True</span>  <span class="c1"># Stub all VCC connections to parts.</span>
</code></pre></div>

<p>The effects of setting these attributes are illustrated using the following code:</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>

<span class="c1"># Create net stubs.</span>
<span class="n">e</span><span class="p">,</span> <span class="n">b</span><span class="p">,</span> <span class="n">c</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s2">&quot;ENET&quot;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s2">&quot;BNET&quot;</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s2">&quot;CNET&quot;</span><span class="p">)</span>
<span class="n">e</span><span class="o">.</span><span class="n">stub</span><span class="p">,</span> <span class="n">b</span><span class="o">.</span><span class="n">stub</span><span class="p">,</span> <span class="n">c</span><span class="o">.</span><span class="n">stub</span> <span class="o">=</span> <span class="kc">True</span><span class="p">,</span> <span class="kc">True</span><span class="p">,</span> <span class="kc">True</span>

<span class="c1"># Create transistor part template.</span>
<span class="n">qt</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="n">lib</span><span class="o">=</span><span class="s2">&quot;Transistor_BJT&quot;</span><span class="p">,</span> <span class="n">name</span><span class="o">=</span><span class="s2">&quot;Q_PNP_CBE&quot;</span><span class="p">,</span> <span class="n">dest</span><span class="o">=</span><span class="n">TEMPLATE</span><span class="p">)</span>

<span class="c1"># Instantiate transistor with various orientations.</span>
<span class="k">for</span> <span class="n">q</span><span class="p">,</span> <span class="n">tx</span> <span class="ow">in</span> <span class="nb">zip</span><span class="p">(</span><span class="n">qt</span><span class="p">(</span><span class="mi">8</span><span class="p">),</span> <span class="p">[</span><span class="s1">&#39;&#39;</span><span class="p">,</span> <span class="s1">&#39;H&#39;</span><span class="p">,</span> <span class="s1">&#39;V&#39;</span><span class="p">,</span> <span class="s1">&#39;R&#39;</span><span class="p">,</span> <span class="s1">&#39;L&#39;</span><span class="p">,</span> <span class="s1">&#39;VL&#39;</span><span class="p">,</span> <span class="s1">&#39;HR&#39;</span><span class="p">,</span> <span class="s1">&#39;LV&#39;</span><span class="p">]):</span>
    <span class="n">q</span><span class="p">[</span><span class="s1">&#39;E B C&#39;</span><span class="p">]</span> <span class="o">+=</span> <span class="n">e</span><span class="p">,</span> <span class="n">b</span><span class="p">,</span> <span class="n">c</span>  <span class="c1"># Attach stubs to transistor pins.</span>
    <span class="n">q</span><span class="o">.</span><span class="n">symtx</span> <span class="o">=</span> <span class="n">tx</span>  <span class="c1"># Assign orientation to transistor attributes.</span>
    <span class="n">q</span><span class="o">.</span><span class="n">ref</span> <span class="o">=</span> <span class="s1">&#39;Q_&#39;</span> <span class="o">+</span> <span class="n">tx</span>  <span class="c1"># Place orientation in transistor reference.</span>

<span class="n">generate_svg</span><span class="p">()</span>
</code></pre></div>

<p>And this is the result:</p>
<p><img alt="And_GATE schematic with transistor orientations and stubs," src="images/symtx_examples.svg"></p>
<h2 id="kicad-schematics">KiCad Schematics</h2>
<p>To generate a schematic file that can be opened with KiCad Eeschema, just append the following to the end of the script:</p>
<div class="highlight"><pre><span></span><code><span class="n">generate_schematic</span><span class="p">()</span>
</code></pre></div>

<p>This will drop an Eeschema file called <code>and_gate_top.sch</code> into the same directory as the <code>and_gate.py</code> file.</p>
<p><img alt="KiCad 5 Eeschema AND_GATE schematic." src="images/and_gate_4.png"></p>
<p>Currently, this file can only be opened using KiCad version 5.
(If you're using a more recent version of KiCad, then there are some
<a href="https://github.com/devbisme/docker_kicad">Docker files for running different versions of KiCad</a> without affecting your current setup.)</p>
<p>The <code>generate_schematic()</code> function accepts these parameters:</p>
<ul>
<li><code>filepath</code> (<code>str</code>, optional): The directory where the schematic files are placed. Defaults to ".".</li>
<li><code>top_name</code> (<code>str</code>, optional): The name for the top of the circuit hierarchy. Defaults to the script name.</li>
<li><code>title</code> (<code>str</code>, optional): The title in the title box of the schematic. Defaults to "SKiDL-Generated Schematic".</li>
<li><code>flatness</code> (<code>float</code>, optional): Determines how much the hierarchy is flattened in the schematic. Defaults to 0.0 (completely hierarchical).</li>
<li><code>retries</code> (<code>int</code>, optional): Number of times to re-try if placement and routing fails. Defaults to 2.</li>
</ul>
<p>In addition, the <code>generate_schematic()</code> function supports the <code>symtx</code> and <code>netio</code> attributes discussed 
in the <a href="#svg-schematics">section on generating SVG schematics</a>.</p>
<h2 id="dot-graphs">DOT Graphs</h2>
<p><strong>Note: Viewing DOT files requires that you install
<a href="https://www.graphviz.org/download/">graphviz</a> on your system.</strong></p>
<p>To generate a DOT file for the circuit, just append the following to the end of the script:</p>
<div class="highlight"><pre><span></span><code><span class="n">generate_dot</span><span class="p">(</span><span class="n">file_</span><span class="o">=</span><span class="s1">&#39;and_gate.dot&#39;</span><span class="p">)</span>
</code></pre></div>

<p>After running the script to generate the <code>and_gate.dot</code> file, you can transform it into
a bitmap file using the command:</p>
<div class="highlight"><pre><span></span><code>$<span class="w"> </span>dot<span class="w"> </span>-Tpng<span class="w"> </span>-Kneato<span class="w"> </span>-O<span class="w"> </span>and_gate.dot
</code></pre></div>

<p>The resulting <code>and_gate.dot.png</code> file looks like this:</p>
<p><img alt="AND_GATE graph." src="images/and_gate.dot.png"></p>
<p>While this might serve as a sanity-check for a small circuit,
it would be indecipherable for a circuit that had
microcontrollers or FPGAs with hundreds of pins!</p>
<h1 id="converting-existing-designs-to-skidl">Converting Existing Designs to SKiDL</h1>
<p><strong>Currently, this feature is only available for KiCad designs.</strong></p>
<p>You can convert an existing schematic-based design to SKiDL like this:</p>
<ol>
<li>
<p>Generate a netlist file for your design using whatever procedure your ECAD
   system provides. For this discussion, call the netlist file <code>my_design.net</code>.</p>
</li>
<li>
<p>Convert the netlist file into a SKiDL script using the following command:</p>
<p><code>terminal
netlist_to_skidl -i my_design.net -o my_design -w</code></p>
</li>
</ol>
<p>That's it! You can execute the <code>main.py</code> script in the <code>my_design</code> directory
and it will regenerate the netlist.
Or you can use the script as a subcircuit in a larger design.
Or do anything else that a SKiDL-based design supports.</p>
<h1 id="spice-simulations">SPICE Simulations</h1>
<p>You can describe a circuit using SKiDL and run a SPICE simulation on it.
Go <a href="https://github.com/devbisme/skidl/blob/master/tests/examples/spice-sim-intro/spice-sim-intro.ipynb">here</a>
to get the complete details.</p>
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